diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-20 17:29:37 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-20 17:29:37 -0500 |
commit | 6db167dfc013b0e114c81077ac091ba26a69f4ed (patch) | |
tree | 1978b8a2774e0fdb3690065625b0b5eb84475552 /arch/arm/include/asm/kvm_arm.h | |
parent | 32f9aab8ebd886211a7b3e552753af014c3e5225 (diff) | |
parent | 9cb543124a2d31af42ce61a4c30765ecc8e5f1fa (diff) |
Merge branch 'for-linus-2' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM updates (part two) from Russell King:
- breakpoint and perf updates from Will Deacon.
- hypervisor boot mode updates from Will.
- support for Power State Coordination Interface via the Hypervisor
- core ARM support for KVM
* 'for-linus-2' of git://git.linaro.org/people/rmk/linux-arm: (32 commits)
KVM: ARM: Add maintainer entry for KVM/ARM
KVM: ARM: Power State Coordination Interface implementation
KVM: ARM: Handle I/O aborts
KVM: ARM: Handle guest faults in KVM
KVM: ARM: VFP userspace interface
KVM: ARM: Demux CCSIDR in the userspace API
KVM: ARM: User space API for getting/setting co-proc registers
KVM: ARM: Emulation framework and CP15 emulation
KVM: ARM: World-switch implementation
KVM: ARM: Inject IRQs and FIQs from userspace
KVM: ARM: Memory virtualization setup
KVM: ARM: Hypervisor initialization
KVM: ARM: Initial skeleton to compile KVM support
ARM: Section based HYP idmap
ARM: Add page table and page defines needed by KVM
ARM: perf: simplify __hw_perf_event_init err handling
ARM: perf: remove unnecessary checks for idx < 0
ARM: perf: handle armpmu_register failing
ARM: perf: don't pretend to support counting of L1I writes
ARM: perf: remove redundant NULL check on cpu_pmu
...
Diffstat (limited to 'arch/arm/include/asm/kvm_arm.h')
-rw-r--r-- | arch/arm/include/asm/kvm_arm.h | 214 |
1 files changed, 214 insertions, 0 deletions
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h new file mode 100644 index 000000000000..7c3d813e15df --- /dev/null +++ b/arch/arm/include/asm/kvm_arm.h | |||
@@ -0,0 +1,214 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | ||
3 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License, version 2, as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
17 | */ | ||
18 | |||
19 | #ifndef __ARM_KVM_ARM_H__ | ||
20 | #define __ARM_KVM_ARM_H__ | ||
21 | |||
22 | #include <linux/types.h> | ||
23 | |||
24 | /* Hyp Configuration Register (HCR) bits */ | ||
25 | #define HCR_TGE (1 << 27) | ||
26 | #define HCR_TVM (1 << 26) | ||
27 | #define HCR_TTLB (1 << 25) | ||
28 | #define HCR_TPU (1 << 24) | ||
29 | #define HCR_TPC (1 << 23) | ||
30 | #define HCR_TSW (1 << 22) | ||
31 | #define HCR_TAC (1 << 21) | ||
32 | #define HCR_TIDCP (1 << 20) | ||
33 | #define HCR_TSC (1 << 19) | ||
34 | #define HCR_TID3 (1 << 18) | ||
35 | #define HCR_TID2 (1 << 17) | ||
36 | #define HCR_TID1 (1 << 16) | ||
37 | #define HCR_TID0 (1 << 15) | ||
38 | #define HCR_TWE (1 << 14) | ||
39 | #define HCR_TWI (1 << 13) | ||
40 | #define HCR_DC (1 << 12) | ||
41 | #define HCR_BSU (3 << 10) | ||
42 | #define HCR_BSU_IS (1 << 10) | ||
43 | #define HCR_FB (1 << 9) | ||
44 | #define HCR_VA (1 << 8) | ||
45 | #define HCR_VI (1 << 7) | ||
46 | #define HCR_VF (1 << 6) | ||
47 | #define HCR_AMO (1 << 5) | ||
48 | #define HCR_IMO (1 << 4) | ||
49 | #define HCR_FMO (1 << 3) | ||
50 | #define HCR_PTW (1 << 2) | ||
51 | #define HCR_SWIO (1 << 1) | ||
52 | #define HCR_VM 1 | ||
53 | |||
54 | /* | ||
55 | * The bits we set in HCR: | ||
56 | * TAC: Trap ACTLR | ||
57 | * TSC: Trap SMC | ||
58 | * TSW: Trap cache operations by set/way | ||
59 | * TWI: Trap WFI | ||
60 | * TIDCP: Trap L2CTLR/L2ECTLR | ||
61 | * BSU_IS: Upgrade barriers to the inner shareable domain | ||
62 | * FB: Force broadcast of all maintainance operations | ||
63 | * AMO: Override CPSR.A and enable signaling with VA | ||
64 | * IMO: Override CPSR.I and enable signaling with VI | ||
65 | * FMO: Override CPSR.F and enable signaling with VF | ||
66 | * SWIO: Turn set/way invalidates into set/way clean+invalidate | ||
67 | */ | ||
68 | #define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ | ||
69 | HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ | ||
70 | HCR_SWIO | HCR_TIDCP) | ||
71 | #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) | ||
72 | |||
73 | /* System Control Register (SCTLR) bits */ | ||
74 | #define SCTLR_TE (1 << 30) | ||
75 | #define SCTLR_EE (1 << 25) | ||
76 | #define SCTLR_V (1 << 13) | ||
77 | |||
78 | /* Hyp System Control Register (HSCTLR) bits */ | ||
79 | #define HSCTLR_TE (1 << 30) | ||
80 | #define HSCTLR_EE (1 << 25) | ||
81 | #define HSCTLR_FI (1 << 21) | ||
82 | #define HSCTLR_WXN (1 << 19) | ||
83 | #define HSCTLR_I (1 << 12) | ||
84 | #define HSCTLR_C (1 << 2) | ||
85 | #define HSCTLR_A (1 << 1) | ||
86 | #define HSCTLR_M 1 | ||
87 | #define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \ | ||
88 | HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE) | ||
89 | |||
90 | /* TTBCR and HTCR Registers bits */ | ||
91 | #define TTBCR_EAE (1 << 31) | ||
92 | #define TTBCR_IMP (1 << 30) | ||
93 | #define TTBCR_SH1 (3 << 28) | ||
94 | #define TTBCR_ORGN1 (3 << 26) | ||
95 | #define TTBCR_IRGN1 (3 << 24) | ||
96 | #define TTBCR_EPD1 (1 << 23) | ||
97 | #define TTBCR_A1 (1 << 22) | ||
98 | #define TTBCR_T1SZ (3 << 16) | ||
99 | #define TTBCR_SH0 (3 << 12) | ||
100 | #define TTBCR_ORGN0 (3 << 10) | ||
101 | #define TTBCR_IRGN0 (3 << 8) | ||
102 | #define TTBCR_EPD0 (1 << 7) | ||
103 | #define TTBCR_T0SZ 3 | ||
104 | #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) | ||
105 | |||
106 | /* Hyp System Trap Register */ | ||
107 | #define HSTR_T(x) (1 << x) | ||
108 | #define HSTR_TTEE (1 << 16) | ||
109 | #define HSTR_TJDBX (1 << 17) | ||
110 | |||
111 | /* Hyp Coprocessor Trap Register */ | ||
112 | #define HCPTR_TCP(x) (1 << x) | ||
113 | #define HCPTR_TCP_MASK (0x3fff) | ||
114 | #define HCPTR_TASE (1 << 15) | ||
115 | #define HCPTR_TTA (1 << 20) | ||
116 | #define HCPTR_TCPAC (1 << 31) | ||
117 | |||
118 | /* Hyp Debug Configuration Register bits */ | ||
119 | #define HDCR_TDRA (1 << 11) | ||
120 | #define HDCR_TDOSA (1 << 10) | ||
121 | #define HDCR_TDA (1 << 9) | ||
122 | #define HDCR_TDE (1 << 8) | ||
123 | #define HDCR_HPME (1 << 7) | ||
124 | #define HDCR_TPM (1 << 6) | ||
125 | #define HDCR_TPMCR (1 << 5) | ||
126 | #define HDCR_HPMN_MASK (0x1F) | ||
127 | |||
128 | /* | ||
129 | * The architecture supports 40-bit IPA as input to the 2nd stage translations | ||
130 | * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address | ||
131 | * space. | ||
132 | */ | ||
133 | #define KVM_PHYS_SHIFT (40) | ||
134 | #define KVM_PHYS_SIZE (1ULL << KVM_PHYS_SHIFT) | ||
135 | #define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL) | ||
136 | #define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30)) | ||
137 | #define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t)) | ||
138 | #define S2_PGD_SIZE (1 << S2_PGD_ORDER) | ||
139 | |||
140 | /* Virtualization Translation Control Register (VTCR) bits */ | ||
141 | #define VTCR_SH0 (3 << 12) | ||
142 | #define VTCR_ORGN0 (3 << 10) | ||
143 | #define VTCR_IRGN0 (3 << 8) | ||
144 | #define VTCR_SL0 (3 << 6) | ||
145 | #define VTCR_S (1 << 4) | ||
146 | #define VTCR_T0SZ (0xf) | ||
147 | #define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \ | ||
148 | VTCR_S | VTCR_T0SZ) | ||
149 | #define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0) | ||
150 | #define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */ | ||
151 | #define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */ | ||
152 | #define KVM_VTCR_SL0 VTCR_SL_L1 | ||
153 | /* stage-2 input address range defined as 2^(32-T0SZ) */ | ||
154 | #define KVM_T0SZ (32 - KVM_PHYS_SHIFT) | ||
155 | #define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ) | ||
156 | #define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S) | ||
157 | |||
158 | /* Virtualization Translation Table Base Register (VTTBR) bits */ | ||
159 | #if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */ | ||
160 | #define VTTBR_X (14 - KVM_T0SZ) | ||
161 | #else | ||
162 | #define VTTBR_X (5 - KVM_T0SZ) | ||
163 | #endif | ||
164 | #define VTTBR_BADDR_SHIFT (VTTBR_X - 1) | ||
165 | #define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) | ||
166 | #define VTTBR_VMID_SHIFT (48LLU) | ||
167 | #define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT) | ||
168 | |||
169 | /* Hyp Syndrome Register (HSR) bits */ | ||
170 | #define HSR_EC_SHIFT (26) | ||
171 | #define HSR_EC (0x3fU << HSR_EC_SHIFT) | ||
172 | #define HSR_IL (1U << 25) | ||
173 | #define HSR_ISS (HSR_IL - 1) | ||
174 | #define HSR_ISV_SHIFT (24) | ||
175 | #define HSR_ISV (1U << HSR_ISV_SHIFT) | ||
176 | #define HSR_SRT_SHIFT (16) | ||
177 | #define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT) | ||
178 | #define HSR_FSC (0x3f) | ||
179 | #define HSR_FSC_TYPE (0x3c) | ||
180 | #define HSR_SSE (1 << 21) | ||
181 | #define HSR_WNR (1 << 6) | ||
182 | #define HSR_CV_SHIFT (24) | ||
183 | #define HSR_CV (1U << HSR_CV_SHIFT) | ||
184 | #define HSR_COND_SHIFT (20) | ||
185 | #define HSR_COND (0xfU << HSR_COND_SHIFT) | ||
186 | |||
187 | #define FSC_FAULT (0x04) | ||
188 | #define FSC_PERM (0x0c) | ||
189 | |||
190 | /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ | ||
191 | #define HPFAR_MASK (~0xf) | ||
192 | |||
193 | #define HSR_EC_UNKNOWN (0x00) | ||
194 | #define HSR_EC_WFI (0x01) | ||
195 | #define HSR_EC_CP15_32 (0x03) | ||
196 | #define HSR_EC_CP15_64 (0x04) | ||
197 | #define HSR_EC_CP14_MR (0x05) | ||
198 | #define HSR_EC_CP14_LS (0x06) | ||
199 | #define HSR_EC_CP_0_13 (0x07) | ||
200 | #define HSR_EC_CP10_ID (0x08) | ||
201 | #define HSR_EC_JAZELLE (0x09) | ||
202 | #define HSR_EC_BXJ (0x0A) | ||
203 | #define HSR_EC_CP14_64 (0x0C) | ||
204 | #define HSR_EC_SVC_HYP (0x11) | ||
205 | #define HSR_EC_HVC (0x12) | ||
206 | #define HSR_EC_SMC (0x13) | ||
207 | #define HSR_EC_IABT (0x20) | ||
208 | #define HSR_EC_IABT_HYP (0x21) | ||
209 | #define HSR_EC_DABT (0x24) | ||
210 | #define HSR_EC_DABT_HYP (0x25) | ||
211 | |||
212 | #define HSR_HVC_IMM_MASK ((1UL << 16) - 1) | ||
213 | |||
214 | #endif /* __ARM_KVM_ARM_H__ */ | ||