diff options
author | Alexander Shishkin <virtuoso@slind.org> | 2010-08-04 06:26:27 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-04 15:20:44 -0400 |
commit | 9f5336915bc47947230290a1a384de95803f815a (patch) | |
tree | a4075dac40d96734b90b83b3e98f88e09bb0263a /arch/arm/include/asm/hardware | |
parent | 8234eaef8002cb8ba30920949b338d692508137a (diff) |
ARM: 6293/1: coresight: cosmetic fixes
Use BIT() macro whenever it is sensible to do so.
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/hardware')
-rw-r--r-- | arch/arm/include/asm/hardware/coresight.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index d84605175fc4..7ecd793b8f5a 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h | |||
@@ -100,10 +100,10 @@ | |||
100 | 100 | ||
101 | /* ETM status register, "ETM Architecture", 3.3.2 */ | 101 | /* ETM status register, "ETM Architecture", 3.3.2 */ |
102 | #define ETMR_STATUS (0x10) | 102 | #define ETMR_STATUS (0x10) |
103 | #define ETMST_OVERFLOW (1 << 0) | 103 | #define ETMST_OVERFLOW BIT(0) |
104 | #define ETMST_PROGBIT (1 << 1) | 104 | #define ETMST_PROGBIT BIT(1) |
105 | #define ETMST_STARTSTOP (1 << 2) | 105 | #define ETMST_STARTSTOP BIT(2) |
106 | #define ETMST_TRIGGER (1 << 3) | 106 | #define ETMST_TRIGGER BIT(3) |
107 | 107 | ||
108 | #define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) | 108 | #define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) |
109 | #define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) | 109 | #define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) |
@@ -111,7 +111,7 @@ | |||
111 | 111 | ||
112 | #define ETMR_TRACEENCTRL2 0x1c | 112 | #define ETMR_TRACEENCTRL2 0x1c |
113 | #define ETMR_TRACEENCTRL 0x24 | 113 | #define ETMR_TRACEENCTRL 0x24 |
114 | #define ETMTE_INCLEXCL (1 << 24) | 114 | #define ETMTE_INCLEXCL BIT(24) |
115 | #define ETMR_TRACEENEVT 0x20 | 115 | #define ETMR_TRACEENEVT 0x20 |
116 | #define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ | 116 | #define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ |
117 | ETMCTRL_DATA_DO_ADDR | \ | 117 | ETMCTRL_DATA_DO_ADDR | \ |
@@ -134,12 +134,12 @@ | |||
134 | #define ETBR_CTRL 0x20 | 134 | #define ETBR_CTRL 0x20 |
135 | #define ETBR_FORMATTERCTRL 0x304 | 135 | #define ETBR_FORMATTERCTRL 0x304 |
136 | #define ETBFF_ENFTC 1 | 136 | #define ETBFF_ENFTC 1 |
137 | #define ETBFF_ENFCONT (1 << 1) | 137 | #define ETBFF_ENFCONT BIT(1) |
138 | #define ETBFF_FONFLIN (1 << 4) | 138 | #define ETBFF_FONFLIN BIT(4) |
139 | #define ETBFF_MANUAL_FLUSH (1 << 6) | 139 | #define ETBFF_MANUAL_FLUSH BIT(6) |
140 | #define ETBFF_TRIGIN (1 << 8) | 140 | #define ETBFF_TRIGIN BIT(8) |
141 | #define ETBFF_TRIGEVT (1 << 9) | 141 | #define ETBFF_TRIGEVT BIT(9) |
142 | #define ETBFF_TRIGFL (1 << 10) | 142 | #define ETBFF_TRIGFL BIT(10) |
143 | 143 | ||
144 | #define etb_writel(t, v, x) \ | 144 | #define etb_writel(t, v, x) \ |
145 | (__raw_writel((v), (t)->etb_regs + (x))) | 145 | (__raw_writel((v), (t)->etb_regs + (x))) |