diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-23 07:12:01 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-02-23 12:24:16 -0500 |
commit | c191789c787f488fdb74de0ee55258f71a427704 (patch) | |
tree | c4cc27449e2ecb9f863c104e5b968b836e64738f /arch/arm/common | |
parent | 617912440bf20497d23d01ab58076998aced3f15 (diff) |
ARM: irq migration: update GIC migration code
This cleans up after the conversion to irq_data. Rename the function
to match the method, and remove the now useless lookup of the irq
descriptor which is never used. Move the bitmask calculation out of
the irq_controller_lock region.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common')
-rw-r--r-- | arch/arm/common/gic.c | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 224377211151..e21c1f4218d3 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -142,25 +142,24 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
142 | } | 142 | } |
143 | 143 | ||
144 | #ifdef CONFIG_SMP | 144 | #ifdef CONFIG_SMP |
145 | static int | 145 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
146 | gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force) | 146 | bool force) |
147 | { | 147 | { |
148 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); | 148 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
149 | unsigned int shift = (d->irq % 4) * 8; | 149 | unsigned int shift = (d->irq % 4) * 8; |
150 | unsigned int cpu = cpumask_first(mask_val); | 150 | unsigned int cpu = cpumask_first(mask_val); |
151 | u32 val; | 151 | u32 val, mask, bit; |
152 | struct irq_desc *desc; | ||
153 | 152 | ||
154 | spin_lock(&irq_controller_lock); | 153 | if (cpu >= 8) |
155 | desc = irq_to_desc(d->irq); | ||
156 | if (desc == NULL) { | ||
157 | spin_unlock(&irq_controller_lock); | ||
158 | return -EINVAL; | 154 | return -EINVAL; |
159 | } | 155 | |
156 | mask = 0xff << shift; | ||
157 | bit = 1 << (cpu + shift); | ||
158 | |||
159 | spin_lock(&irq_controller_lock); | ||
160 | d->node = cpu; | 160 | d->node = cpu; |
161 | val = readl(reg) & ~(0xff << shift); | 161 | val = readl(reg) & ~mask; |
162 | val |= 1 << (cpu + shift); | 162 | writel(val | bit, reg); |
163 | writel(val, reg); | ||
164 | spin_unlock(&irq_controller_lock); | 163 | spin_unlock(&irq_controller_lock); |
165 | 164 | ||
166 | return 0; | 165 | return 0; |
@@ -203,7 +202,7 @@ static struct irq_chip gic_chip = { | |||
203 | .irq_unmask = gic_unmask_irq, | 202 | .irq_unmask = gic_unmask_irq, |
204 | .irq_set_type = gic_set_type, | 203 | .irq_set_type = gic_set_type, |
205 | #ifdef CONFIG_SMP | 204 | #ifdef CONFIG_SMP |
206 | .irq_set_affinity = gic_set_cpu, | 205 | .irq_set_affinity = gic_set_affinity, |
207 | #endif | 206 | #endif |
208 | }; | 207 | }; |
209 | 208 | ||