diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-05-23 14:28:04 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-05-23 14:28:04 -0400 |
commit | 9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0 (patch) | |
tree | 894bb6a3fb409c6ac5f0374f5a1f656918bc35cd /arch/arm/common | |
parent | ec19628d72cff8f80220b7cedba089074ac6a599 (diff) | |
parent | dc7ad3b3d5f1cd0a0d16c05dd3ad3898979d261e (diff) |
Merge branch 'devel-stable' into for-linus
Conflicts:
arch/arm/Kconfig
arch/arm/mach-ns9xxx/include/mach/uncompress.h
Diffstat (limited to 'arch/arm/common')
-rw-r--r-- | arch/arm/common/gic.c | 84 |
1 files changed, 45 insertions, 39 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index f70ec7dadebb..4ddd0a6ac7ff 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -49,7 +49,7 @@ struct gic_chip_data { | |||
49 | * Default make them NULL. | 49 | * Default make them NULL. |
50 | */ | 50 | */ |
51 | struct irq_chip gic_arch_extn = { | 51 | struct irq_chip gic_arch_extn = { |
52 | .irq_ack = NULL, | 52 | .irq_eoi = NULL, |
53 | .irq_mask = NULL, | 53 | .irq_mask = NULL, |
54 | .irq_unmask = NULL, | 54 | .irq_unmask = NULL, |
55 | .irq_retrigger = NULL, | 55 | .irq_retrigger = NULL, |
@@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d) | |||
84 | /* | 84 | /* |
85 | * Routines to acknowledge, disable and enable interrupts | 85 | * Routines to acknowledge, disable and enable interrupts |
86 | */ | 86 | */ |
87 | static void gic_ack_irq(struct irq_data *d) | ||
88 | { | ||
89 | spin_lock(&irq_controller_lock); | ||
90 | if (gic_arch_extn.irq_ack) | ||
91 | gic_arch_extn.irq_ack(d); | ||
92 | writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); | ||
93 | spin_unlock(&irq_controller_lock); | ||
94 | } | ||
95 | |||
96 | static void gic_mask_irq(struct irq_data *d) | 87 | static void gic_mask_irq(struct irq_data *d) |
97 | { | 88 | { |
98 | u32 mask = 1 << (d->irq % 32); | 89 | u32 mask = 1 << (d->irq % 32); |
99 | 90 | ||
100 | spin_lock(&irq_controller_lock); | 91 | spin_lock(&irq_controller_lock); |
101 | writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); | 92 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
102 | if (gic_arch_extn.irq_mask) | 93 | if (gic_arch_extn.irq_mask) |
103 | gic_arch_extn.irq_mask(d); | 94 | gic_arch_extn.irq_mask(d); |
104 | spin_unlock(&irq_controller_lock); | 95 | spin_unlock(&irq_controller_lock); |
@@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d) | |||
111 | spin_lock(&irq_controller_lock); | 102 | spin_lock(&irq_controller_lock); |
112 | if (gic_arch_extn.irq_unmask) | 103 | if (gic_arch_extn.irq_unmask) |
113 | gic_arch_extn.irq_unmask(d); | 104 | gic_arch_extn.irq_unmask(d); |
114 | writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); | 105 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
115 | spin_unlock(&irq_controller_lock); | 106 | spin_unlock(&irq_controller_lock); |
116 | } | 107 | } |
117 | 108 | ||
109 | static void gic_eoi_irq(struct irq_data *d) | ||
110 | { | ||
111 | if (gic_arch_extn.irq_eoi) { | ||
112 | spin_lock(&irq_controller_lock); | ||
113 | gic_arch_extn.irq_eoi(d); | ||
114 | spin_unlock(&irq_controller_lock); | ||
115 | } | ||
116 | |||
117 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); | ||
118 | } | ||
119 | |||
118 | static int gic_set_type(struct irq_data *d, unsigned int type) | 120 | static int gic_set_type(struct irq_data *d, unsigned int type) |
119 | { | 121 | { |
120 | void __iomem *base = gic_dist_base(d); | 122 | void __iomem *base = gic_dist_base(d); |
@@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
138 | if (gic_arch_extn.irq_set_type) | 140 | if (gic_arch_extn.irq_set_type) |
139 | gic_arch_extn.irq_set_type(d, type); | 141 | gic_arch_extn.irq_set_type(d, type); |
140 | 142 | ||
141 | val = readl(base + GIC_DIST_CONFIG + confoff); | 143 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
142 | if (type == IRQ_TYPE_LEVEL_HIGH) | 144 | if (type == IRQ_TYPE_LEVEL_HIGH) |
143 | val &= ~confmask; | 145 | val &= ~confmask; |
144 | else if (type == IRQ_TYPE_EDGE_RISING) | 146 | else if (type == IRQ_TYPE_EDGE_RISING) |
@@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
148 | * As recommended by the spec, disable the interrupt before changing | 150 | * As recommended by the spec, disable the interrupt before changing |
149 | * the configuration | 151 | * the configuration |
150 | */ | 152 | */ |
151 | if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { | 153 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
152 | writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); | 154 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); |
153 | enabled = true; | 155 | enabled = true; |
154 | } | 156 | } |
155 | 157 | ||
156 | writel(val, base + GIC_DIST_CONFIG + confoff); | 158 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
157 | 159 | ||
158 | if (enabled) | 160 | if (enabled) |
159 | writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); | 161 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
160 | 162 | ||
161 | spin_unlock(&irq_controller_lock); | 163 | spin_unlock(&irq_controller_lock); |
162 | 164 | ||
@@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |||
188 | 190 | ||
189 | spin_lock(&irq_controller_lock); | 191 | spin_lock(&irq_controller_lock); |
190 | d->node = cpu; | 192 | d->node = cpu; |
191 | val = readl(reg) & ~mask; | 193 | val = readl_relaxed(reg) & ~mask; |
192 | writel(val | bit, reg); | 194 | writel_relaxed(val | bit, reg); |
193 | spin_unlock(&irq_controller_lock); | 195 | spin_unlock(&irq_controller_lock); |
194 | 196 | ||
195 | return 0; | 197 | return 0; |
@@ -218,11 +220,10 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |||
218 | unsigned int cascade_irq, gic_irq; | 220 | unsigned int cascade_irq, gic_irq; |
219 | unsigned long status; | 221 | unsigned long status; |
220 | 222 | ||
221 | /* primary controller ack'ing */ | 223 | chained_irq_enter(chip, desc); |
222 | chip->irq_ack(&desc->irq_data); | ||
223 | 224 | ||
224 | spin_lock(&irq_controller_lock); | 225 | spin_lock(&irq_controller_lock); |
225 | status = readl(chip_data->cpu_base + GIC_CPU_INTACK); | 226 | status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); |
226 | spin_unlock(&irq_controller_lock); | 227 | spin_unlock(&irq_controller_lock); |
227 | 228 | ||
228 | gic_irq = (status & 0x3ff); | 229 | gic_irq = (status & 0x3ff); |
@@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |||
236 | generic_handle_irq(cascade_irq); | 237 | generic_handle_irq(cascade_irq); |
237 | 238 | ||
238 | out: | 239 | out: |
239 | /* primary controller unmasking */ | 240 | chained_irq_exit(chip, desc); |
240 | chip->irq_unmask(&desc->irq_data); | ||
241 | } | 241 | } |
242 | 242 | ||
243 | static struct irq_chip gic_chip = { | 243 | static struct irq_chip gic_chip = { |
244 | .name = "GIC", | 244 | .name = "GIC", |
245 | .irq_ack = gic_ack_irq, | ||
246 | .irq_mask = gic_mask_irq, | 245 | .irq_mask = gic_mask_irq, |
247 | .irq_unmask = gic_unmask_irq, | 246 | .irq_unmask = gic_unmask_irq, |
247 | .irq_eoi = gic_eoi_irq, | ||
248 | .irq_set_type = gic_set_type, | 248 | .irq_set_type = gic_set_type, |
249 | .irq_retrigger = gic_retrigger, | 249 | .irq_retrigger = gic_retrigger, |
250 | #ifdef CONFIG_SMP | 250 | #ifdef CONFIG_SMP |
@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic, | |||
272 | cpumask |= cpumask << 8; | 272 | cpumask |= cpumask << 8; |
273 | cpumask |= cpumask << 16; | 273 | cpumask |= cpumask << 16; |
274 | 274 | ||
275 | writel(0, base + GIC_DIST_CTRL); | 275 | writel_relaxed(0, base + GIC_DIST_CTRL); |
276 | 276 | ||
277 | /* | 277 | /* |
278 | * Find out how many interrupts are supported. | 278 | * Find out how many interrupts are supported. |
279 | * The GIC only supports up to 1020 interrupt sources. | 279 | * The GIC only supports up to 1020 interrupt sources. |
280 | */ | 280 | */ |
281 | gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; | 281 | gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f; |
282 | gic_irqs = (gic_irqs + 1) * 32; | 282 | gic_irqs = (gic_irqs + 1) * 32; |
283 | if (gic_irqs > 1020) | 283 | if (gic_irqs > 1020) |
284 | gic_irqs = 1020; | 284 | gic_irqs = 1020; |
@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic, | |||
287 | * Set all global interrupts to be level triggered, active low. | 287 | * Set all global interrupts to be level triggered, active low. |
288 | */ | 288 | */ |
289 | for (i = 32; i < gic_irqs; i += 16) | 289 | for (i = 32; i < gic_irqs; i += 16) |
290 | writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); | 290 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
291 | 291 | ||
292 | /* | 292 | /* |
293 | * Set all global interrupts to this CPU only. | 293 | * Set all global interrupts to this CPU only. |
294 | */ | 294 | */ |
295 | for (i = 32; i < gic_irqs; i += 4) | 295 | for (i = 32; i < gic_irqs; i += 4) |
296 | writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); | 296 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
297 | 297 | ||
298 | /* | 298 | /* |
299 | * Set priority on all global interrupts. | 299 | * Set priority on all global interrupts. |
300 | */ | 300 | */ |
301 | for (i = 32; i < gic_irqs; i += 4) | 301 | for (i = 32; i < gic_irqs; i += 4) |
302 | writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); | 302 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
303 | 303 | ||
304 | /* | 304 | /* |
305 | * Disable all interrupts. Leave the PPI and SGIs alone | 305 | * Disable all interrupts. Leave the PPI and SGIs alone |
306 | * as these enables are banked registers. | 306 | * as these enables are banked registers. |
307 | */ | 307 | */ |
308 | for (i = 32; i < gic_irqs; i += 32) | 308 | for (i = 32; i < gic_irqs; i += 32) |
309 | writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); | 309 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
310 | 310 | ||
311 | /* | 311 | /* |
312 | * Limit number of interrupts registered to the platform maximum | 312 | * Limit number of interrupts registered to the platform maximum |
@@ -319,12 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic, | |||
319 | * Setup the Linux IRQ subsystem. | 319 | * Setup the Linux IRQ subsystem. |
320 | */ | 320 | */ |
321 | for (i = irq_start; i < irq_limit; i++) { | 321 | for (i = irq_start; i < irq_limit; i++) { |
322 | irq_set_chip_and_handler(i, &gic_chip, handle_level_irq); | 322 | irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); |
323 | irq_set_chip_data(i, gic); | 323 | irq_set_chip_data(i, gic); |
324 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 324 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
325 | } | 325 | } |
326 | 326 | ||
327 | writel(1, base + GIC_DIST_CTRL); | 327 | writel_relaxed(1, base + GIC_DIST_CTRL); |
328 | } | 328 | } |
329 | 329 | ||
330 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) | 330 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) | |||
337 | * Deal with the banked PPI and SGI interrupts - disable all | 337 | * Deal with the banked PPI and SGI interrupts - disable all |
338 | * PPI interrupts, ensure all SGI interrupts are enabled. | 338 | * PPI interrupts, ensure all SGI interrupts are enabled. |
339 | */ | 339 | */ |
340 | writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); | 340 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
341 | writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | 341 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); |
342 | 342 | ||
343 | /* | 343 | /* |
344 | * Set priority on PPI and SGI interrupts | 344 | * Set priority on PPI and SGI interrupts |
345 | */ | 345 | */ |
346 | for (i = 0; i < 32; i += 4) | 346 | for (i = 0; i < 32; i += 4) |
347 | writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); | 347 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
348 | 348 | ||
349 | writel(0xf0, base + GIC_CPU_PRIMASK); | 349 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
350 | writel(1, base + GIC_CPU_CTRL); | 350 | writel_relaxed(1, base + GIC_CPU_CTRL); |
351 | } | 351 | } |
352 | 352 | ||
353 | void __init gic_init(unsigned int gic_nr, unsigned int irq_start, | 353 | void __init gic_init(unsigned int gic_nr, unsigned int irq_start, |
@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |||
391 | { | 391 | { |
392 | unsigned long map = *cpus_addr(*mask); | 392 | unsigned long map = *cpus_addr(*mask); |
393 | 393 | ||
394 | /* | ||
395 | * Ensure that stores to Normal memory are visible to the | ||
396 | * other CPUs before issuing the IPI. | ||
397 | */ | ||
398 | dsb(); | ||
399 | |||
394 | /* this always happens on GIC0 */ | 400 | /* this always happens on GIC0 */ |
395 | writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); | 401 | writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); |
396 | } | 402 | } |
397 | #endif | 403 | #endif |