diff options
author | Rob Herring <r.herring@freescale.com> | 2010-10-06 11:18:08 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-11-04 11:49:32 -0400 |
commit | 8a9618f5dfca35edb0d7ab6374ff586e2e9e989b (patch) | |
tree | 0104c5a164af6f750aee1dd2e86c6c0b333d004a /arch/arm/common | |
parent | ff8b16d7e15a8ba2a6086645614a483e048e3fbf (diff) |
ARM: 6432/1: move timer-sp.c from versatile to common
From: Rob Herring <rob.herring@smooth-stone.com>
The timer-sp h/w used on versatile platforms can also be used for other
platforms, so move it to a common location.
Signed-off-by: Rob Herring <rob.herring@smooth-stone.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common')
-rw-r--r-- | arch/arm/common/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/common/timer-sp.c | 154 |
2 files changed, 155 insertions, 0 deletions
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e6e8664a9413..e7521bca2c35 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile | |||
@@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_IXP2000) += uengine.o | |||
17 | obj-$(CONFIG_ARCH_IXP23XX) += uengine.o | 17 | obj-$(CONFIG_ARCH_IXP23XX) += uengine.o |
18 | obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o | 18 | obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o |
19 | obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o | 19 | obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o |
20 | obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o | ||
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c new file mode 100644 index 000000000000..4740313daa5b --- /dev/null +++ b/arch/arm/common/timer-sp.c | |||
@@ -0,0 +1,154 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/common/timer-sp.c | ||
3 | * | ||
4 | * Copyright (C) 1999 - 2003 ARM Limited | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #include <linux/clocksource.h> | ||
22 | #include <linux/clockchips.h> | ||
23 | #include <linux/interrupt.h> | ||
24 | #include <linux/irq.h> | ||
25 | #include <linux/io.h> | ||
26 | |||
27 | #include <asm/hardware/arm_timer.h> | ||
28 | |||
29 | /* | ||
30 | * These timers are currently always setup to be clocked at 1MHz. | ||
31 | */ | ||
32 | #define TIMER_FREQ_KHZ (1000) | ||
33 | #define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) | ||
34 | |||
35 | static void __iomem *clksrc_base; | ||
36 | |||
37 | static cycle_t sp804_read(struct clocksource *cs) | ||
38 | { | ||
39 | return ~readl(clksrc_base + TIMER_VALUE); | ||
40 | } | ||
41 | |||
42 | static struct clocksource clocksource_sp804 = { | ||
43 | .name = "timer3", | ||
44 | .rating = 200, | ||
45 | .read = sp804_read, | ||
46 | .mask = CLOCKSOURCE_MASK(32), | ||
47 | .shift = 20, | ||
48 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
49 | }; | ||
50 | |||
51 | void __init sp804_clocksource_init(void __iomem *base) | ||
52 | { | ||
53 | struct clocksource *cs = &clocksource_sp804; | ||
54 | |||
55 | clksrc_base = base; | ||
56 | |||
57 | /* setup timer 0 as free-running clocksource */ | ||
58 | writel(0, clksrc_base + TIMER_CTRL); | ||
59 | writel(0xffffffff, clksrc_base + TIMER_LOAD); | ||
60 | writel(0xffffffff, clksrc_base + TIMER_VALUE); | ||
61 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | ||
62 | clksrc_base + TIMER_CTRL); | ||
63 | |||
64 | cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift); | ||
65 | clocksource_register(cs); | ||
66 | } | ||
67 | |||
68 | |||
69 | static void __iomem *clkevt_base; | ||
70 | |||
71 | /* | ||
72 | * IRQ handler for the timer | ||
73 | */ | ||
74 | static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) | ||
75 | { | ||
76 | struct clock_event_device *evt = dev_id; | ||
77 | |||
78 | /* clear the interrupt */ | ||
79 | writel(1, clkevt_base + TIMER_INTCLR); | ||
80 | |||
81 | evt->event_handler(evt); | ||
82 | |||
83 | return IRQ_HANDLED; | ||
84 | } | ||
85 | |||
86 | static void sp804_set_mode(enum clock_event_mode mode, | ||
87 | struct clock_event_device *evt) | ||
88 | { | ||
89 | unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE; | ||
90 | |||
91 | writel(ctrl, clkevt_base + TIMER_CTRL); | ||
92 | |||
93 | switch (mode) { | ||
94 | case CLOCK_EVT_MODE_PERIODIC: | ||
95 | writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); | ||
96 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; | ||
97 | break; | ||
98 | |||
99 | case CLOCK_EVT_MODE_ONESHOT: | ||
100 | /* period set, and timer enabled in 'next_event' hook */ | ||
101 | ctrl |= TIMER_CTRL_ONESHOT; | ||
102 | break; | ||
103 | |||
104 | case CLOCK_EVT_MODE_UNUSED: | ||
105 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
106 | default: | ||
107 | break; | ||
108 | } | ||
109 | |||
110 | writel(ctrl, clkevt_base + TIMER_CTRL); | ||
111 | } | ||
112 | |||
113 | static int sp804_set_next_event(unsigned long next, | ||
114 | struct clock_event_device *evt) | ||
115 | { | ||
116 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | ||
117 | |||
118 | writel(next, clkevt_base + TIMER_LOAD); | ||
119 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | static struct clock_event_device sp804_clockevent = { | ||
125 | .name = "timer0", | ||
126 | .shift = 32, | ||
127 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
128 | .set_mode = sp804_set_mode, | ||
129 | .set_next_event = sp804_set_next_event, | ||
130 | .rating = 300, | ||
131 | .cpumask = cpu_all_mask, | ||
132 | }; | ||
133 | |||
134 | static struct irqaction sp804_timer_irq = { | ||
135 | .name = "timer", | ||
136 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
137 | .handler = sp804_timer_interrupt, | ||
138 | .dev_id = &sp804_clockevent, | ||
139 | }; | ||
140 | |||
141 | void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) | ||
142 | { | ||
143 | struct clock_event_device *evt = &sp804_clockevent; | ||
144 | |||
145 | clkevt_base = base; | ||
146 | |||
147 | evt->irq = timer_irq; | ||
148 | evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); | ||
149 | evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); | ||
150 | evt->min_delta_ns = clockevent_delta2ns(0xf, evt); | ||
151 | |||
152 | setup_irq(timer_irq, &sp804_timer_irq); | ||
153 | clockevents_register_device(evt); | ||
154 | } | ||