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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:31:31 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:31:31 -0400
commitf01b9b73f57f4f92d39bba0d9aa4a38f318212df (patch)
treeb815a4477af34f7f6c61dff0c04db6cb975cdd55 /arch/arm/boot
parentfde75430278130505cac21997cd9f90b7bb2670a (diff)
parent66314223aa5e862c9d1d068cb7186b4fd58ebeaa (diff)
Merge tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull support for three new arm SoC types from Arnd Bergmann: - The mvebu platform includes Marvell's Armada XP and Armada 370 chips, made by the mvebu business unit inside of Marvell. Since the same group also made the older but similar platforms we call "orion5x", "kirkwood", "mv78xx0" and "dove", we plan to move all of them into the mach-mvebu directory in the future. - socfpga is Altera's platform based on Cortex-A9 cores and a lot of FPGA space. This is similar to the Xilinx zynq platform we already support. The code is particularly clean, which is helped by the fact that the hardware doesn't do much besides the parts that are expected to get added in the FPGA. - The OMAP subarchitecture gains support for the latest generation, the OMAP5 based on the new Cortex-A15 core. Support is rather rudimentary for now, but will be extended in the future. * tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits) ARM: socfpga: initial support for Altera's SOCFPGA platform arm: mvebu: generate DTBs for supported SoCs ARM: mvebu: MPIC: read number of interrupts from control register arm: mach-mvebu: add entry to MAINTAINERS arm: mach-mvebu: add compilation/configuration change arm: mach-mvebu: add defconfig arm: mach-mvebu: add documentation for new device tree bindings arm: mach-mvebu: add support for Armada 370 and Armada XP with DT arm: mach-mvebu: add source files arm: mach-mvebu: add header clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver ARM: Kconfig update to support additional GPIOs in OMAP5 ARM: OMAP5: Add the build support arm/dts: OMAP5: Add omap5 dts files ARM: OMAP5: board-generic: Add device tree support ARM: omap2+: board-generic: clean up the irq data from board file ARM: OMAP5: Add SMP support ARM: OMAP5: Add the WakeupGen IP updates ARM: OMAP5: l3: Add l3 error handler support for omap5 ARM: OMAP5: gpmc: Update gpmc_init() ... Conflicts: Documentation/devicetree/bindings/arm/omap/omap.txt arch/arm/mach-omap2/Makefile drivers/clocksource/Kconfig drivers/clocksource/Makefile
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts42
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi68
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi35
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts50
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi55
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts20
-rw-r--r--arch/arm/boot/dts/omap5.dtsi184
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi147
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dts34
9 files changed, 635 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
new file mode 100644
index 000000000000..fffd5c2a3041
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -0,0 +1,42 @@
1/*
2 * Device Tree file for Marvell Armada 370 evaluation board
3 * (DB-88F6710-BP-DDR3)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-370.dtsi"
18
19/ {
20 model = "Marvell Armada 370 Evaluation Board";
21 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x20000000>; /* 512 MB */
30 };
31
32 soc {
33 serial@d0012000 {
34 clock-frequency = <200000000>;
35 status = "okay";
36 };
37 timer@d0020300 {
38 clock-frequency = <600000000>;
39 status = "okay";
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
new file mode 100644
index 000000000000..6b6b932a5a7d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -0,0 +1,68 @@
1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada_370_xp";
24
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 };
38
39 soc {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
43 interrupt-parent = <&mpic>;
44 ranges;
45
46 serial@d0012000 {
47 compatible = "ns16550";
48 reg = <0xd0012000 0x100>;
49 reg-shift = <2>;
50 interrupts = <41>;
51 status = "disabled";
52 };
53 serial@d0012100 {
54 compatible = "ns16550";
55 reg = <0xd0012100 0x100>;
56 reg-shift = <2>;
57 interrupts = <42>;
58 status = "disabled";
59 };
60
61 timer@d0020300 {
62 compatible = "marvell,armada-370-xp-timer";
63 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>;
65 };
66 };
67};
68
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
new file mode 100644
index 000000000000..3228ccc83332
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
16 */
17
18/include/ "armada-370-xp.dtsi"
19
20/ {
21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23
24 mpic: interrupt-controller@d0020000 {
25 reg = <0xd0020a00 0x1d0>,
26 <0xd0021870 0x58>;
27 };
28
29 soc {
30 system-controller@d0018200 {
31 compatible = "marvell,armada-370-xp-system-controller";
32 reg = <0xd0018200 0x100>;
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
new file mode 100644
index 000000000000..f97040d4258d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -0,0 +1,50 @@
1/*
2 * Device Tree file for Marvell Armada XP evaluation board
3 * (DB-78460-BP)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-xp.dtsi"
18
19/ {
20 model = "Marvell Armada XP Evaluation Board";
21 compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x80000000>; /* 2 GB */
30 };
31
32 soc {
33 serial@d0012000 {
34 clock-frequency = <250000000>;
35 status = "okay";
36 };
37 serial@d0012100 {
38 clock-frequency = <250000000>;
39 status = "okay";
40 };
41 serial@d0012200 {
42 clock-frequency = <250000000>;
43 status = "okay";
44 };
45 serial@d0012300 {
46 clock-frequency = <250000000>;
47 status = "okay";
48 };
49 };
50};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
new file mode 100644
index 000000000000..e1fa7e6edfe8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -0,0 +1,55 @@
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada 370 SoC that are not
16 * common to all Armada SoCs.
17 */
18
19/include/ "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 mpic: interrupt-controller@d0020000 {
26 reg = <0xd0020a00 0x1d0>,
27 <0xd0021870 0x58>;
28 };
29
30 soc {
31 serial@d0012200 {
32 compatible = "ns16550";
33 reg = <0xd0012200 0x100>;
34 reg-shift = <2>;
35 interrupts = <43>;
36 status = "disabled";
37 };
38 serial@d0012300 {
39 compatible = "ns16550";
40 reg = <0xd0012300 0x100>;
41 reg-shift = <2>;
42 interrupts = <44>;
43 status = "disabled";
44 };
45
46 timer@d0020300 {
47 marvell,timer-25Mhz;
48 };
49
50 system-controller@d0018200 {
51 compatible = "marvell,armada-370-xp-system-controller";
52 reg = <0xd0018200 0x500>;
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
new file mode 100644
index 000000000000..200c39ad1c82
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap5.dtsi"
11
12/ {
13 model = "TI OMAP5 EVM board";
14 compatible = "ti,omap5-evm", "ti,omap5";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 };
20};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
new file mode 100644
index 000000000000..57e527083746
--- /dev/null
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -0,0 +1,184 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10/*
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
15 */
16/memreserve/ 0x9d000000 0x03000000;
17
18/include/ "skeleton.dtsi"
19
20/ {
21 compatible = "ti,omap5";
22 interrupt-parent = <&gic>;
23
24 aliases {
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 serial4 = &uart5;
30 serial5 = &uart6;
31 };
32
33 cpus {
34 cpu@0 {
35 compatible = "arm,cortex-a15";
36 };
37 cpu@1 {
38 compatible = "arm,cortex-a15";
39 };
40 };
41
42 /*
43 * The soc node represents the soc top level view. It is uses for IPs
44 * that are not memory mapped in the MPU view or for the MPU itself.
45 */
46 soc {
47 compatible = "ti,omap-infra";
48 mpu {
49 compatible = "ti,omap5-mpu";
50 ti,hwmods = "mpu";
51 };
52 };
53
54 /*
55 * XXX: Use a flat representation of the OMAP3 interconnect.
56 * The real OMAP interconnect network is quite complex.
57 * Since that will not bring real advantage to represent that in DT for
58 * the moment, just use a fake OCP bus entry to represent the whole bus
59 * hierarchy.
60 */
61 ocp {
62 compatible = "ti,omap4-l3-noc", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges;
66 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
67
68 gic: interrupt-controller@48211000 {
69 compatible = "arm,cortex-a15-gic";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x48211000 0x1000>,
73 <0x48212000 0x1000>;
74 };
75
76 gpio1: gpio@4ae10000 {
77 compatible = "ti,omap4-gpio";
78 ti,hwmods = "gpio1";
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupt-cells = <1>;
83 };
84
85 gpio2: gpio@48055000 {
86 compatible = "ti,omap4-gpio";
87 ti,hwmods = "gpio2";
88 gpio-controller;
89 #gpio-cells = <2>;
90 interrupt-controller;
91 #interrupt-cells = <1>;
92 };
93
94 gpio3: gpio@48057000 {
95 compatible = "ti,omap4-gpio";
96 ti,hwmods = "gpio3";
97 gpio-controller;
98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupt-cells = <1>;
101 };
102
103 gpio4: gpio@48059000 {
104 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio4";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 };
111
112 gpio5: gpio@4805b000 {
113 compatible = "ti,omap4-gpio";
114 ti,hwmods = "gpio5";
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <1>;
119 };
120
121 gpio6: gpio@4805d000 {
122 compatible = "ti,omap4-gpio";
123 ti,hwmods = "gpio6";
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 };
129
130 gpio7: gpio@48051000 {
131 compatible = "ti,omap4-gpio";
132 ti,hwmods = "gpio7";
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
137 };
138
139 gpio8: gpio@48053000 {
140 compatible = "ti,omap4-gpio";
141 ti,hwmods = "gpio8";
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <1>;
146 };
147
148 uart1: serial@4806a000 {
149 compatible = "ti,omap4-uart";
150 ti,hwmods = "uart1";
151 clock-frequency = <48000000>;
152 };
153
154 uart2: serial@4806c000 {
155 compatible = "ti,omap4-uart";
156 ti,hwmods = "uart2";
157 clock-frequency = <48000000>;
158 };
159
160 uart3: serial@48020000 {
161 compatible = "ti,omap4-uart";
162 ti,hwmods = "uart3";
163 clock-frequency = <48000000>;
164 };
165
166 uart4: serial@4806e000 {
167 compatible = "ti,omap4-uart";
168 ti,hwmods = "uart4";
169 clock-frequency = <48000000>;
170 };
171
172 uart5: serial@48066000 {
173 compatible = "ti,omap5-uart";
174 ti,hwmods = "uart5";
175 clock-frequency = <48000000>;
176 };
177
178 uart6: serial@48068000 {
179 compatible = "ti,omap6-uart";
180 ti,hwmods = "uart6";
181 clock-frequency = <48000000>;
182 };
183 };
184};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644
index 000000000000..0772f5739f59
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "skeleton.dtsi"
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 intc: intc@fffed000 {
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
51 interrupt-controller;
52 reg = <0xfffed000 0x1000>,
53 <0xfffec100 0x100>;
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
60 device_type = "soc";
61 interrupt-parent = <&intc>;
62 ranges;
63
64 amba {
65 compatible = "arm,amba-bus";
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
69
70 pdma: pdma@ffe01000 {
71 compatible = "arm,pl330", "arm,primecell";
72 reg = <0xffe01000 0x1000>;
73 interrupts = <0 180 4>;
74 };
75 };
76
77 gmac0: stmmac@ff700000 {
78 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
79 reg = <0xff700000 0x2000>;
80 interrupts = <0 115 4>;
81 interrupt-names = "macirq";
82 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
83 phy-mode = "gmii";
84 };
85
86 L2: l2-cache@fffef000 {
87 compatible = "arm,pl310-cache";
88 reg = <0xfffef000 0x1000>;
89 interrupts = <0 38 0x04>;
90 cache-unified;
91 cache-level = <2>;
92 };
93
94 /* Local timer */
95 timer@fffec600 {
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0xfffec600 0x100>;
98 interrupts = <1 13 0xf04>;
99 };
100
101 timer0: timer@ffc08000 {
102 compatible = "snps,dw-apb-timer-sp";
103 interrupts = <0 167 4>;
104 clock-frequency = <200000000>;
105 reg = <0xffc08000 0x1000>;
106 };
107
108 timer1: timer@ffc09000 {
109 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 168 4>;
111 clock-frequency = <200000000>;
112 reg = <0xffc09000 0x1000>;
113 };
114
115 timer2: timer@ffd00000 {
116 compatible = "snps,dw-apb-timer-osc";
117 interrupts = <0 169 4>;
118 clock-frequency = <200000000>;
119 reg = <0xffd00000 0x1000>;
120 };
121
122 timer3: timer@ffd01000 {
123 compatible = "snps,dw-apb-timer-osc";
124 interrupts = <0 170 4>;
125 clock-frequency = <200000000>;
126 reg = <0xffd01000 0x1000>;
127 };
128
129 uart0: uart@ffc02000 {
130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>;
132 clock-frequency = <7372800>;
133 interrupts = <0 162 4>;
134 reg-shift = <2>;
135 reg-io-width = <4>;
136 };
137
138 uart1: uart@ffc03000 {
139 compatible = "snps,dw-apb-uart";
140 reg = <0xffc03000 0x1000>;
141 clock-frequency = <7372800>;
142 interrupts = <0 163 4>;
143 reg-shift = <2>;
144 reg-io-width = <4>;
145 };
146 };
147};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
new file mode 100644
index 000000000000..ab7e4a94299f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/include/ "socfpga.dtsi"
20
21/ {
22 model = "Altera SOCFPGA Cyclone V";
23 compatible = "altr,socfpga-cyclone5";
24
25 chosen {
26 bootargs = "console=ttyS0,57600";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x10000000>; /* 256MB */
33 };
34};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 15:32:20 -0500