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authorBoris BREZILLON <b.brezillon@overkiz.com>2013-08-07 04:49:01 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2013-10-16 09:47:08 -0400
commitd7d1d45cc46d79ab9227288e225aa51078855729 (patch)
treea2cd1cb9d532439e35628eb631cbce9c981ba05a /arch/arm/boot
parentd195608acc78db293468694ed5225a39e440429d (diff)
ARM: at91/dt: split sama5d3 peripheral definitions
This patch splits the sama5d3 SoCs definition: - a common base for all sama5d3 SoCs (sama5d3.dtsi) - several optional peripheral definitions which will be included by sama5d3 specific SoCs (sama5d3_'periph name'.dtsi) - sama5d3 specific SoC definitions (sama5d3x.dtsi) This provides a better representation of the real hardware (drop unneed dt nodes) and avoids peripheral id conflict (which is not the case for current sama5d3 SoCs, but could be if other SoCs of this family are released). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> [nicolas.ferre@atmel.com: add more "sama5d3?" compatibility strings] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi203
-rw-r--r--arch/arm/boot/dts/sama5d31.dtsi16
-rw-r--r--arch/arm/boot/dts/sama5d31ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d33.dtsi14
-rw-r--r--arch/arm/boot/dts/sama5d33ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d34.dtsi16
-rw-r--r--arch/arm/boot/dts/sama5d34ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d35.dtsi18
-rw-r--r--arch/arm/boot/dts/sama5d35ek.dts3
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi54
-rw-r--r--arch/arm/boot/dts/sama5d3_emac.dtsi44
-rw-r--r--arch/arm/boot/dts/sama5d3_gmac.dtsi77
-rw-r--r--arch/arm/boot/dts/sama5d3_lcd.dtsi55
-rw-r--r--arch/arm/boot/dts/sama5d3_mci2.dtsi47
-rw-r--r--arch/arm/boot/dts/sama5d3_tcb1.dtsi27
-rw-r--r--arch/arm/boot/dts/sama5d3_uart.dtsi53
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi1
17 files changed, 429 insertions, 208 deletions
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index b7f49615120d..5cdaba4cea86 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -31,7 +31,6 @@
31 gpio3 = &pioD; 31 gpio3 = &pioD;
32 gpio4 = &pioE; 32 gpio4 = &pioE;
33 tcb0 = &tcb0; 33 tcb0 = &tcb0;
34 tcb1 = &tcb1;
35 i2c0 = &i2c0; 34 i2c0 = &i2c0;
36 i2c1 = &i2c1; 35 i2c1 = &i2c1;
37 i2c2 = &i2c2; 36 i2c2 = &i2c2;
@@ -105,15 +104,6 @@
105 status = "disabled"; 104 status = "disabled";
106 }; 105 };
107 106
108 can0: can@f000c000 {
109 compatible = "atmel,at91sam9x5-can";
110 reg = <0xf000c000 0x300>;
111 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_can0_rx_tx>;
114 status = "disabled";
115 };
116
117 tcb0: timer@f0010000 { 107 tcb0: timer@f0010000 {
118 compatible = "atmel,at91sam9x5-tcb"; 108 compatible = "atmel,at91sam9x5-tcb";
119 reg = <0xf0010000 0x100>; 109 reg = <0xf0010000 0x100>;
@@ -166,15 +156,6 @@
166 status = "disabled"; 156 status = "disabled";
167 }; 157 };
168 158
169 macb0: ethernet@f0028000 {
170 compatible = "cdns,pc302-gem", "cdns,gem";
171 reg = <0xf0028000 0x100>;
172 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
175 status = "disabled";
176 };
177
178 isi: isi@f0034000 { 159 isi: isi@f0034000 {
179 compatible = "atmel,at91sam9g45-isi"; 160 compatible = "atmel,at91sam9g45-isi";
180 reg = <0xf0034000 0x4000>; 161 reg = <0xf0034000 0x4000>;
@@ -195,19 +176,6 @@
195 #size-cells = <0>; 176 #size-cells = <0>;
196 }; 177 };
197 178
198 mmc2: mmc@f8004000 {
199 compatible = "atmel,hsmci";
200 reg = <0xf8004000 0x600>;
201 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
202 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
203 dma-names = "rxtx";
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
206 status = "disabled";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210
211 spi1: spi@f8008000 { 179 spi1: spi@f8008000 {
212 #address-cells = <1>; 180 #address-cells = <1>;
213 #size-cells = <0>; 181 #size-cells = <0>;
@@ -231,20 +199,6 @@
231 status = "disabled"; 199 status = "disabled";
232 }; 200 };
233 201
234 can1: can@f8010000 {
235 compatible = "atmel,at91sam9x5-can";
236 reg = <0xf8010000 0x300>;
237 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_can1_rx_tx>;
240 };
241
242 tcb1: timer@f8014000 {
243 compatible = "atmel,at91sam9x5-tcb";
244 reg = <0xf8014000 0x100>;
245 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
246 };
247
248 adc0: adc@f8018000 { 202 adc0: adc@f8018000 {
249 compatible = "atmel,at91sam9260-adc"; 203 compatible = "atmel,at91sam9260-adc";
250 reg = <0xf8018000 0x100>; 204 reg = <0xf8018000 0x100>;
@@ -341,15 +295,6 @@
341 status = "disabled"; 295 status = "disabled";
342 }; 296 };
343 297
344 macb1: ethernet@f802c000 {
345 compatible = "cdns,at32ap7000-macb", "cdns,macb";
346 reg = <0xf802c000 0x100>;
347 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_macb1_rmii>;
350 status = "disabled";
351 };
352
353 sha@f8034000 { 298 sha@f8034000 {
354 compatible = "atmel,sam9g46-sha"; 299 compatible = "atmel,sam9g46-sha";
355 reg = <0xf8034000 0x100>; 300 reg = <0xf8034000 0x100>;
@@ -474,22 +419,6 @@
474 }; 419 };
475 }; 420 };
476 421
477 can0 {
478 pinctrl_can0_rx_tx: can0_rx_tx {
479 atmel,pins =
480 <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
481 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
482 };
483 };
484
485 can1 {
486 pinctrl_can1_rx_tx: can1_rx_tx {
487 atmel,pins =
488 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
489 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
490 };
491 };
492
493 dbgu { 422 dbgu {
494 pinctrl_dbgu: dbgu-0 { 423 pinctrl_dbgu: dbgu-0 {
495 atmel,pins = 424 atmel,pins =
@@ -537,107 +466,6 @@
537 }; 466 };
538 }; 467 };
539 468
540 lcd {
541 pinctrl_lcd: lcd-0 {
542 atmel,pins =
543 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
544 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
545 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
546 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
547 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
548 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
549 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
550 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
551 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
552 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
553 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
554 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
555 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
556 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
557 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
558 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
559 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
560 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
561 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
562 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
563 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
564 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
565 AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
566 AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
567 AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
568 AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
569 AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
570 AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
571 AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
572 AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
573 };
574 };
575
576 macb0 {
577 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
578 atmel,pins =
579 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
580 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
581 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
582 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
583 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
584 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
585 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
586 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
587 };
588 pinctrl_macb0_data_gmii: macb0_data_gmii {
589 atmel,pins =
590 <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
591 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
592 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
593 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
594 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
595 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
596 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
597 AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
598 };
599 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
600 atmel,pins =
601 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
602 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
603 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
604 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
605 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
606 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
607 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
608 };
609 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
610 atmel,pins =
611 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
612 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
613 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
614 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
615 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
616 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
617 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
618 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
619 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
620 AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
621 };
622
623 };
624
625 macb1 {
626 pinctrl_macb1_rmii: macb1_rmii-0 {
627 atmel,pins =
628 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
629 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
630 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
631 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
632 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
633 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
634 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
635 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
636 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
637 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
638 };
639 };
640
641 mmc0 { 469 mmc0 {
642 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 470 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
643 atmel,pins = 471 atmel,pins =
@@ -675,21 +503,6 @@
675 }; 503 };
676 }; 504 };
677 505
678 mmc2 {
679 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
680 atmel,pins =
681 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
682 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
683 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
684 };
685 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
686 atmel,pins =
687 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
688 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
689 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
690 };
691 };
692
693 nand0 { 506 nand0 {
694 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 507 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
695 atmel,pins = 508 atmel,pins =
@@ -748,22 +561,6 @@
748 }; 561 };
749 }; 562 };
750 563
751 uart0 {
752 pinctrl_uart0: uart0-0 {
753 atmel,pins =
754 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
755 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
756 };
757 };
758
759 uart1 {
760 pinctrl_uart1: uart1-0 {
761 atmel,pins =
762 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
763 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
764 };
765 };
766
767 usart0 { 564 usart0 {
768 pinctrl_usart0: usart0-0 { 565 pinctrl_usart0: usart0-0 {
769 atmel,pins = 566 atmel,pins =
diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi
new file mode 100644
index 000000000000..7997dc9863ed
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d31.dtsi
@@ -0,0 +1,16 @@
1/*
2 * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_lcd.dtsi"
10#include "sama5d3_emac.dtsi"
11#include "sama5d3_mci2.dtsi"
12#include "sama5d3_uart.dtsi"
13
14/ {
15 compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5";
16};
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 027bac7510b6..04eec0dfcf7d 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -7,12 +7,13 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d31.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11#include "sama5d3xdm.dtsi" 12#include "sama5d3xdm.dtsi"
12 13
13/ { 14/ {
14 model = "Atmel SAMA5D31-EK"; 15 model = "Atmel SAMA5D31-EK";
15 compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
16 17
17 ahb { 18 ahb {
18 apb { 19 apb {
diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi
new file mode 100644
index 000000000000..39f832253caf
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d33.dtsi
@@ -0,0 +1,14 @@
1/*
2 * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_lcd.dtsi"
10#include "sama5d3_gmac.dtsi"
11
12/ {
13 compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5";
14};
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index 99bd0c8e0471..cbd6a3ff1545 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -7,12 +7,13 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d33.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11#include "sama5d3xdm.dtsi" 12#include "sama5d3xdm.dtsi"
12 13
13/ { 14/ {
14 model = "Atmel SAMA5D33-EK"; 15 model = "Atmel SAMA5D33-EK";
15 compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
16 17
17 ahb { 18 ahb {
18 apb { 19 apb {
diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi
new file mode 100644
index 000000000000..89cda2c0da39
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d34.dtsi
@@ -0,0 +1,16 @@
1/*
2 * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_lcd.dtsi"
10#include "sama5d3_gmac.dtsi"
11#include "sama5d3_can.dtsi"
12#include "sama5d3_mci2.dtsi"
13
14/ {
15 compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5";
16};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index fb8ee11cf282..878aa164275a 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -7,12 +7,13 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d34.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11#include "sama5d3xdm.dtsi" 12#include "sama5d3xdm.dtsi"
12 13
13/ { 14/ {
14 model = "Atmel SAMA5D34-EK"; 15 model = "Atmel SAMA5D34-EK";
15 compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
16 17
17 ahb { 18 ahb {
18 apb { 19 apb {
diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi
new file mode 100644
index 000000000000..d20cd71b5f0e
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d35.dtsi
@@ -0,0 +1,18 @@
1/*
2 * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include "sama5d3.dtsi"
9#include "sama5d3_gmac.dtsi"
10#include "sama5d3_emac.dtsi"
11#include "sama5d3_can.dtsi"
12#include "sama5d3_mci2.dtsi"
13#include "sama5d3_uart.dtsi"
14#include "sama5d3_tcb1.dtsi"
15
16/ {
17 compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5";
18};
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 509a53d9cc7b..9089c7c6cea8 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -7,11 +7,12 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "sama5d35.dtsi"
10#include "sama5d3xmb.dtsi" 11#include "sama5d3xmb.dtsi"
11 12
12/ { 13/ {
13 model = "Atmel SAMA5D35-EK"; 14 model = "Atmel SAMA5D35-EK";
14 compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 15 compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
15 16
16 ahb { 17 ahb {
17 apb { 18 apb {
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
new file mode 100644
index 000000000000..8ed3260cef66
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -0,0 +1,54 @@
1/*
2 * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * CAN support
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 can0 {
18 pinctrl_can0_rx_tx: can0_rx_tx {
19 atmel,pins =
20 <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
21 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
22 };
23 };
24
25 can1 {
26 pinctrl_can1_rx_tx: can1_rx_tx {
27 atmel,pins =
28 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
29 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
30 };
31 };
32
33 };
34
35 can0: can@f000c000 {
36 compatible = "atmel,at91sam9x5-can";
37 reg = <0xf000c000 0x300>;
38 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_can0_rx_tx>;
41 status = "disabled";
42 };
43
44 can1: can@f8010000 {
45 compatible = "atmel,at91sam9x5-can";
46 reg = <0xf8010000 0x300>;
47 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_can1_rx_tx>;
50 status = "disabled";
51 };
52 };
53 };
54};
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
new file mode 100644
index 000000000000..4d4f351f1f9f
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -0,0 +1,44 @@
1/*
2 * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * Ethernet.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 macb1 {
18 pinctrl_macb1_rmii: macb1_rmii-0 {
19 atmel,pins =
20 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
21 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
22 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
23 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
24 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
25 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
26 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
27 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
28 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
29 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
30 };
31 };
32 };
33
34 macb1: ethernet@f802c000 {
35 compatible = "cdns,at32ap7000-macb", "cdns,macb";
36 reg = <0xf802c000 0x100>;
37 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_macb1_rmii>;
40 status = "disabled";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
new file mode 100644
index 000000000000..0ba8be30ccd8
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -0,0 +1,77 @@
1/*
2 * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * Gigabit Ethernet.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 macb0 {
18 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
19 atmel,pins =
20 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
21 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
22 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
23 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
24 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
25 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
26 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
27 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
28 };
29 pinctrl_macb0_data_gmii: macb0_data_gmii {
30 atmel,pins =
31 <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
32 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
33 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
34 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
35 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
36 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
37 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
38 AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
39 };
40 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
41 atmel,pins =
42 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
43 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
44 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
45 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
46 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
47 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
48 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
49 };
50 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
51 atmel,pins =
52 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
53 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
54 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
55 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
56 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
57 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
58 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
59 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
60 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
61 AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
62 };
63
64 };
65 };
66
67 macb0: ethernet@f0028000 {
68 compatible = "cdns,pc302-gem", "cdns,gem";
69 reg = <0xf0028000 0x100>;
70 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
73 status = "disabled";
74 };
75 };
76 };
77};
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
new file mode 100644
index 000000000000..01f52a79f8ba
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -0,0 +1,55 @@
1/*
2 * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * LCD support
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 lcd {
18 pinctrl_lcd: lcd-0 {
19 atmel,pins =
20 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
21 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
22 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
23 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
24 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
25 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
26 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
27 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
28 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
29 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
30 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
31 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
32 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
33 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
34 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
35 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
36 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
37 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
38 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
39 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
40 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
41 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
42 AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
43 AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
44 AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
45 AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
46 AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
47 AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
48 AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
49 AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
50 };
51 };
52 };
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
new file mode 100644
index 000000000000..38e88e39e551
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -0,0 +1,47 @@
1/*
2 * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * 3 MMC ports
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 mmc2 {
18 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
19 atmel,pins =
20 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
21 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
22 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
23 };
24 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
25 atmel,pins =
26 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
27 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
28 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
29 };
30 };
31 };
32
33 mmc2: mmc@f8004000 {
34 compatible = "atmel,hsmci";
35 reg = <0xf8004000 0x600>;
36 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
37 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
38 dma-names = "rxtx";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
41 status = "disabled";
42 #address-cells = <1>;
43 #size-cells = <0>;
44 };
45 };
46 };
47};
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
new file mode 100644
index 000000000000..5264bb4a6998
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -0,0 +1,27 @@
1/*
2 * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * 2 TC blocks.
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 aliases {
15 tcb1 = &tcb1;
16 };
17
18 ahb {
19 apb {
20 tcb1: timer@f8014000 {
21 compatible = "atmel,at91sam9x5-tcb";
22 reg = <0xf8014000 0x100>;
23 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
24 };
25 };
26 };
27};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
new file mode 100644
index 000000000000..98fcb2d57446
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -0,0 +1,53 @@
1/*
2 * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
3 * UART support
4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 ahb {
15 apb {
16 pinctrl@fffff200 {
17 uart0 {
18 pinctrl_uart0: uart0-0 {
19 atmel,pins =
20 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
21 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
22 };
23 };
24
25 uart1 {
26 pinctrl_uart1: uart1-0 {
27 atmel,pins =
28 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
29 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
30 };
31 };
32 };
33
34 uart0: serial@f0024000 {
35 compatible = "atmel,at91sam9260-usart";
36 reg = <0xf0024000 0x200>;
37 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart0>;
40 status = "disabled";
41 };
42
43 uart1: serial@f8028000 {
44 compatible = "atmel,at91sam9260-usart";
45 reg = <0xf8028000 0x200>;
46 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart1>;
49 status = "disabled";
50 };
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 31ed9e3bb649..726a0f35100c 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -6,7 +6,6 @@
6 * 6 *
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9#include "sama5d3.dtsi"
10 9
11/ { 10/ {
12 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; 11 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 08:14:23 -0500