Merge tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

Merge "Samsung fixes-3 for 3.16" from Kukjin Kim:

Samsung fixes-3 for v3.16
- update the parent for Auudss clock because kernel will be hang
  during late boot if the parent clock is disabled in bootloader.
- enable clk handing in power domain because while power domain
  on/off, its regarding clock source will be reset and it causes
  a problem so need to handle it.
- add mux clocks to be used by power domain for exynos5420-mfc
  during power domain on/off and property in device tree also.
- register cpuidle only for exynos4210 and exynos5250 because a
  system failure will be happened on other exynos SoCs.

* tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
  ARM: dts: Add clock property for mfc_pd in exynos5420
  clk: exynos5420: Add IDs for clocks used in PD mfc
  ARM: EXYNOS: Add support for clock handling in power domain
  ARM: dts: Update the parent for Audss clocks in Exynos5420

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 4 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e38532271ef9..15957227ffda 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
                 compatible = "samsung,exynos5420-audss-clock";
                 reg = <0x03810000 0x0C>;
                 #clock-cells = <1>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
         };
@@ -260,6 +260,9 @@
         mfc_pd: power-domain@10044060 {
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10044060 0x20>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+                        <&clock CLK_MOUT_USER_ACLK333>;
+                clock-names = "oscclk", "pclk0", "clk0";
         };
 
         disp_pd: power-domain@100440C0 {