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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-02-13 04:14:58 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-03-19 03:31:48 -0400
commitc368dbe2de0a7fec2488eb7e4dcccfe25714ed2b (patch)
tree413544b96925040497ea365ac49d694423538928 /arch/arm/boot
parent64a900ff4727c93e076e814c917f68c225c9b630 (diff)
ARM: dts: use ti,fixed-factor-clock for dpll4_m4x2_mul_ck
We need to use set-rate-parent for dpll4_m4 clock path, so use the ti,fixed-factor-clock version which supports set-rate-parent property. The set-rate-parent flag itself is set in the following patch, this one just changes the clock driver to ti,fixed-factor-clock without any other changes. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Tested-by: Marek Belisko <marek@goldelico.com> Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/omap36xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi6
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index 0b2df76b9d38..6b5280d04a0e 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -79,7 +79,7 @@
79}; 79};
80 80
81&dpll4_m4x2_mul_ck { 81&dpll4_m4x2_mul_ck {
82 clock-mult = <1>; 82 ti,clock-mult = <1>;
83}; 83};
84 84
85&dpll4_m5x2_mul_ck { 85&dpll4_m5x2_mul_ck {
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index cb04d4b37e7f..df3c699a1893 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -425,10 +425,10 @@
425 425
426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { 426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
427 #clock-cells = <0>; 427 #clock-cells = <0>;
428 compatible = "fixed-factor-clock"; 428 compatible = "ti,fixed-factor-clock";
429 clocks = <&dpll4_m4_ck>; 429 clocks = <&dpll4_m4_ck>;
430 clock-mult = <2>; 430 ti,clock-mult = <2>;
431 clock-div = <1>; 431 ti,clock-div = <1>;
432 }; 432 };
433 433
434 dpll4_m4x2_ck: dpll4_m4x2_ck { 434 dpll4_m4x2_ck: dpll4_m4x2_ck {