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authorOlof Johansson <olof@lixom.net>2013-06-07 20:51:39 -0400
committerOlof Johansson <olof@lixom.net>2013-06-07 20:52:38 -0400
commit94937fff01fdeff2f2bd36f739d9cb80c775ed50 (patch)
tree9111c29b0468d8490fe3194d94948fb96772bdd6 /arch/arm/boot
parent54edc2524d0b3c60d7ff6fe2b779acfcc401c45b (diff)
parente36572b64df358f0bc3a508e8761c81d7f3b8215 (diff)
Merge tag 'vt8500/dts-3.11' of git://github.com/linux-wmt/linux-vtwm into next/dt
From Tony Prisk, vt8500 devicetree updates for 3.11. * tag 'vt8500/dts-3.11' of git://github.com/linux-wmt/linux-vtwm: dts: vt8500: Correct reference clock on WM8850 SoCs dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files dts: vt8500: Populate missing PLL nodes dts: clk: vt8500: Update SoC dtsi to use WM8850 PLL clocks dts: vt8500: Update serial nodes and disable by default in SoC files dts: vt8500: Add devicetree support for WM8750 SoC and APC8750 board dts: vt8500: Fix invalid/missing cpu nodes for soc files. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/vt8500-bv07.dts4
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi29
-rw-r--r--arch/arm/boot/dts/wm8505-ref.dts4
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi84
-rw-r--r--arch/arm/boot/dts/wm8650-mid.dts3
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi79
-rw-r--r--arch/arm/boot/dts/wm8750-apc8750.dts30
-rw-r--r--arch/arm/boot/dts/wm8750.dtsi347
-rw-r--r--arch/arm/boot/dts/wm8850-w70v2.dts4
-rw-r--r--arch/arm/boot/dts/wm8850.dtsi94
11 files changed, 649 insertions, 30 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4e8576cb3bf..3107b408a2f6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -211,6 +211,7 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
211dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ 211dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
212 wm8505-ref.dtb \ 212 wm8505-ref.dtb \
213 wm8650-mid.dtb \ 213 wm8650-mid.dtb \
214 wm8750-apc8750.dtb \
214 wm8850-w70v2.dtb 215 wm8850-w70v2.dtb
215dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb 216dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
216 217
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
index 877b33afa7ed..87f33310e2bc 100644
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -30,3 +30,7 @@
30 }; 30 };
31 }; 31 };
32}; 32};
33
34&uart0 {
35 status = "okay";
36};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 4a4b96f6827e..51d0e912c8f5 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -11,6 +11,23 @@
11/ { 11/ {
12 compatible = "via,vt8500"; 12 compatible = "via,vt8500";
13 13
14 cpus {
15 #address-cells = <0>;
16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm926ej-s";
21 };
22 };
23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 };
30
14 soc { 31 soc {
15 #address-cells = <1>; 32 #address-cells = <1>;
16 #size-cells = <1>; 33 #size-cells = <1>;
@@ -111,32 +128,36 @@
111 reg = <0xd8050400 0x100>; 128 reg = <0xd8050400 0x100>;
112 }; 129 };
113 130
114 uart@d8200000 { 131 uart0: serial@d8200000 {
115 compatible = "via,vt8500-uart"; 132 compatible = "via,vt8500-uart";
116 reg = <0xd8200000 0x1040>; 133 reg = <0xd8200000 0x1040>;
117 interrupts = <32>; 134 interrupts = <32>;
118 clocks = <&clkuart0>; 135 clocks = <&clkuart0>;
136 status = "disabled";
119 }; 137 };
120 138
121 uart@d82b0000 { 139 uart1: serial@d82b0000 {
122 compatible = "via,vt8500-uart"; 140 compatible = "via,vt8500-uart";
123 reg = <0xd82b0000 0x1040>; 141 reg = <0xd82b0000 0x1040>;
124 interrupts = <33>; 142 interrupts = <33>;
125 clocks = <&clkuart1>; 143 clocks = <&clkuart1>;
144 status = "disabled";
126 }; 145 };
127 146
128 uart@d8210000 { 147 uart2: serial@d8210000 {
129 compatible = "via,vt8500-uart"; 148 compatible = "via,vt8500-uart";
130 reg = <0xd8210000 0x1040>; 149 reg = <0xd8210000 0x1040>;
131 interrupts = <47>; 150 interrupts = <47>;
132 clocks = <&clkuart2>; 151 clocks = <&clkuart2>;
152 status = "disabled";
133 }; 153 };
134 154
135 uart@d82c0000 { 155 uart3: serial@d82c0000 {
136 compatible = "via,vt8500-uart"; 156 compatible = "via,vt8500-uart";
137 reg = <0xd82c0000 0x1040>; 157 reg = <0xd82c0000 0x1040>;
138 interrupts = <50>; 158 interrupts = <50>;
139 clocks = <&clkuart3>; 159 clocks = <&clkuart3>;
160 status = "disabled";
140 }; 161 };
141 162
142 rtc@d8100000 { 163 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
index edd2cec3d37f..e3e6b9eb09d0 100644
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -30,3 +30,7 @@
30 }; 30 };
31 }; 31 };
32}; 32};
33
34&uart0 {
35 status = "okay";
36};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index b2bf359e852f..a1a854b8a454 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -12,11 +12,24 @@
12 compatible = "wm,wm8505"; 12 compatible = "wm,wm8505";
13 13
14 cpus { 14 cpus {
15 cpu@0 { 15 #address-cells = <0>;
16 compatible = "arm,arm926ejs"; 16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm926ej-s";
17 }; 21 };
18 }; 22 };
19 23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
31 };
32
20 soc { 33 soc {
21 #address-cells = <1>; 34 #address-cells = <1>;
22 #size-cells = <1>; 35 #size-cells = <1>;
@@ -68,6 +81,13 @@
68 clock-frequency = <25000000>; 81 clock-frequency = <25000000>;
69 }; 82 };
70 83
84 plla: plla {
85 #clock-cells = <0>;
86 compatible = "via,vt8500-pll-clock";
87 clocks = <&ref25>;
88 reg = <0x200>;
89 };
90
71 pllb: pllb { 91 pllb: pllb {
72 #clock-cells = <0>; 92 #clock-cells = <0>;
73 compatible = "via,vt8500-pll-clock"; 93 compatible = "via,vt8500-pll-clock";
@@ -75,6 +95,48 @@
75 reg = <0x204>; 95 reg = <0x204>;
76 }; 96 };
77 97
98 pllc: pllc {
99 #clock-cells = <0>;
100 compatible = "via,vt8500-pll-clock";
101 clocks = <&ref25>;
102 reg = <0x208>;
103 };
104
105 plld: plld {
106 #clock-cells = <0>;
107 compatible = "via,vt8500-pll-clock";
108 clocks = <&ref25>;
109 reg = <0x20c>;
110 };
111
112 clkarm: arm {
113 #clock-cells = <0>;
114 compatible = "via,vt8500-device-clock";
115 clocks = <&plla>;
116 divisor-reg = <0x300>;
117 };
118
119 clkahb: ahb {
120 #clock-cells = <0>;
121 compatible = "via,vt8500-device-clock";
122 clocks = <&pllb>;
123 divisor-reg = <0x304>;
124 };
125
126 clkapb: apb {
127 #clock-cells = <0>;
128 compatible = "via,vt8500-device-clock";
129 clocks = <&pllb>;
130 divisor-reg = <0x350>;
131 };
132
133 clkddr: ddr {
134 #clock-cells = <0>;
135 compatible = "via,vt8500-device-clock";
136 clocks = <&plld>;
137 divisor-reg = <0x310>;
138 };
139
78 clkuart0: uart0 { 140 clkuart0: uart0 {
79 #clock-cells = <0>; 141 #clock-cells = <0>;
80 compatible = "via,vt8500-device-clock"; 142 compatible = "via,vt8500-device-clock";
@@ -163,46 +225,52 @@
163 reg = <0xd8050400 0x100>; 225 reg = <0xd8050400 0x100>;
164 }; 226 };
165 227
166 uart@d8200000 { 228 uart0: serial@d8200000 {
167 compatible = "via,vt8500-uart"; 229 compatible = "via,vt8500-uart";
168 reg = <0xd8200000 0x1040>; 230 reg = <0xd8200000 0x1040>;
169 interrupts = <32>; 231 interrupts = <32>;
170 clocks = <&clkuart0>; 232 clocks = <&clkuart0>;
233 status = "disabled";
171 }; 234 };
172 235
173 uart@d82b0000 { 236 uart1: serial@d82b0000 {
174 compatible = "via,vt8500-uart"; 237 compatible = "via,vt8500-uart";
175 reg = <0xd82b0000 0x1040>; 238 reg = <0xd82b0000 0x1040>;
176 interrupts = <33>; 239 interrupts = <33>;
177 clocks = <&clkuart1>; 240 clocks = <&clkuart1>;
241 status = "disabled";
178 }; 242 };
179 243
180 uart@d8210000 { 244 uart2: serial@d8210000 {
181 compatible = "via,vt8500-uart"; 245 compatible = "via,vt8500-uart";
182 reg = <0xd8210000 0x1040>; 246 reg = <0xd8210000 0x1040>;
183 interrupts = <47>; 247 interrupts = <47>;
184 clocks = <&clkuart2>; 248 clocks = <&clkuart2>;
249 status = "disabled";
185 }; 250 };
186 251
187 uart@d82c0000 { 252 uart3: serial@d82c0000 {
188 compatible = "via,vt8500-uart"; 253 compatible = "via,vt8500-uart";
189 reg = <0xd82c0000 0x1040>; 254 reg = <0xd82c0000 0x1040>;
190 interrupts = <50>; 255 interrupts = <50>;
191 clocks = <&clkuart3>; 256 clocks = <&clkuart3>;
257 status = "disabled";
192 }; 258 };
193 259
194 uart@d8370000 { 260 uart4: serial@d8370000 {
195 compatible = "via,vt8500-uart"; 261 compatible = "via,vt8500-uart";
196 reg = <0xd8370000 0x1040>; 262 reg = <0xd8370000 0x1040>;
197 interrupts = <31>; 263 interrupts = <31>;
198 clocks = <&clkuart4>; 264 clocks = <&clkuart4>;
265 status = "disabled";
199 }; 266 };
200 267
201 uart@d8380000 { 268 uart5: serial@d8380000 {
202 compatible = "via,vt8500-uart"; 269 compatible = "via,vt8500-uart";
203 reg = <0xd8380000 0x1040>; 270 reg = <0xd8380000 0x1040>;
204 interrupts = <30>; 271 interrupts = <30>;
205 clocks = <&clkuart5>; 272 clocks = <&clkuart5>;
273 status = "disabled";
206 }; 274 };
207 275
208 rtc@d8100000 { 276 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
index 61671a0d9ede..dd0d1b602388 100644
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -32,3 +32,6 @@
32 }; 32 };
33}; 33};
34 34
35&uart0 {
36 status = "okay";
37};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index dd8464eeb40d..7525982262ac 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -11,6 +11,21 @@
11/ { 11/ {
12 compatible = "wm,wm8650"; 12 compatible = "wm,wm8650";
13 13
14 cpus {
15 #address-cells = <0>;
16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm926ej-s";
21 };
22 };
23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
28
14 soc { 29 soc {
15 #address-cells = <1>; 30 #address-cells = <1>;
16 #size-cells = <1>; 31 #size-cells = <1>;
@@ -77,6 +92,55 @@
77 reg = <0x204>; 92 reg = <0x204>;
78 }; 93 };
79 94
95 pllc: pllc {
96 #clock-cells = <0>;
97 compatible = "wm,wm8650-pll-clock";
98 clocks = <&ref25>;
99 reg = <0x208>;
100 };
101
102 plld: plld {
103 #clock-cells = <0>;
104 compatible = "wm,wm8650-pll-clock";
105 clocks = <&ref25>;
106 reg = <0x20c>;
107 };
108
109 plle: plle {
110 #clock-cells = <0>;
111 compatible = "wm,wm8650-pll-clock";
112 clocks = <&ref25>;
113 reg = <0x210>;
114 };
115
116 clkarm: arm {
117 #clock-cells = <0>;
118 compatible = "via,vt8500-device-clock";
119 clocks = <&plla>;
120 divisor-reg = <0x300>;
121 };
122
123 clkahb: ahb {
124 #clock-cells = <0>;
125 compatible = "via,vt8500-device-clock";
126 clocks = <&pllb>;
127 divisor-reg = <0x304>;
128 };
129
130 clkapb: apb {
131 #clock-cells = <0>;
132 compatible = "via,vt8500-device-clock";
133 clocks = <&pllb>;
134 divisor-reg = <0x320>;
135 };
136
137 clkddr: ddr {
138 #clock-cells = <0>;
139 compatible = "via,vt8500-device-clock";
140 clocks = <&plld>;
141 divisor-reg = <0x310>;
142 };
143
80 clkuart0: uart0 { 144 clkuart0: uart0 {
81 #clock-cells = <0>; 145 #clock-cells = <0>;
82 compatible = "via,vt8500-device-clock"; 146 compatible = "via,vt8500-device-clock";
@@ -93,14 +157,7 @@
93 enable-bit = <2>; 157 enable-bit = <2>;
94 }; 158 };
95 159
96 arm: arm { 160 clksdhc: sdhc {
97 #clock-cells = <0>;
98 compatible = "via,vt8500-device-clock";
99 clocks = <&plla>;
100 divisor-reg = <0x300>;
101 };
102
103 sdhc: sdhc {
104 #clock-cells = <0>; 161 #clock-cells = <0>;
105 compatible = "via,vt8500-device-clock"; 162 compatible = "via,vt8500-device-clock";
106 clocks = <&pllb>; 163 clocks = <&pllb>;
@@ -140,18 +197,20 @@
140 reg = <0xd8050400 0x100>; 197 reg = <0xd8050400 0x100>;
141 }; 198 };
142 199
143 uart@d8200000 { 200 uart0: serial@d8200000 {
144 compatible = "via,vt8500-uart"; 201 compatible = "via,vt8500-uart";
145 reg = <0xd8200000 0x1040>; 202 reg = <0xd8200000 0x1040>;
146 interrupts = <32>; 203 interrupts = <32>;
147 clocks = <&clkuart0>; 204 clocks = <&clkuart0>;
205 status = "disabled";
148 }; 206 };
149 207
150 uart@d82b0000 { 208 uart1: serial@d82b0000 {
151 compatible = "via,vt8500-uart"; 209 compatible = "via,vt8500-uart";
152 reg = <0xd82b0000 0x1040>; 210 reg = <0xd82b0000 0x1040>;
153 interrupts = <33>; 211 interrupts = <33>;
154 clocks = <&clkuart1>; 212 clocks = <&clkuart1>;
213 status = "disabled";
155 }; 214 };
156 215
157 rtc@d8100000 { 216 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts
new file mode 100644
index 000000000000..37e4a408bf39
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750-apc8750.dts
@@ -0,0 +1,30 @@
1/*
2 * wm8750-apc8750.dts
3 * - Device tree file for VIA APC8750
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 *
7 * Licensed under GPLv2 or later
8 */
9
10/dts-v1/;
11/include/ "wm8750.dtsi"
12
13/ {
14 model = "VIA APC8750";
15};
16
17&pinctrl {
18 pinctrl-names = "default";
19 pinctrl-0 = <&i2c>;
20
21 i2c: i2c {
22 wm,pins = <168 169 170 171>;
23 wm,function = <2>; /* alt */
24 wm,pull = <2>; /* pull-up */
25 };
26};
27
28&uart0 {
29 status = "okay";
30};
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi
new file mode 100644
index 000000000000..557a9c2ace49
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -0,0 +1,347 @@
1/*
2 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8750";
13
14 cpus {
15 #address-cells = <0>;
16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm1176ej-s";
21 };
22 };
23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
31 i2c0 = &i2c_0;
32 i2c1 = &i2c_1;
33 };
34
35 soc {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "simple-bus";
39 ranges;
40 interrupt-parent = <&intc0>;
41
42 intc0: interrupt-controller@d8140000 {
43 compatible = "via,vt8500-intc";
44 interrupt-controller;
45 reg = <0xd8140000 0x10000>;
46 #interrupt-cells = <1>;
47 };
48
49 /* Secondary IC cascaded to intc0 */
50 intc1: interrupt-controller@d8150000 {
51 compatible = "via,vt8500-intc";
52 interrupt-controller;
53 #interrupt-cells = <1>;
54 reg = <0xD8150000 0x10000>;
55 interrupts = <56 57 58 59 60 61 62 63>;
56 };
57
58 pinctrl: pinctrl@d8110000 {
59 compatible = "wm,wm8750-pinctrl";
60 reg = <0xd8110000 0x10000>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 };
66
67 pmc@d8130000 {
68 compatible = "via,vt8500-pmc";
69 reg = <0xd8130000 0x1000>;
70
71 clocks {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 ref24: ref24M {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
79 };
80
81 ref25: ref25M {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <25000000>;
85 };
86
87 plla: plla {
88 #clock-cells = <0>;
89 compatible = "wm,wm8750-pll-clock";
90 clocks = <&ref25>;
91 reg = <0x200>;
92 };
93
94 pllb: pllb {
95 #clock-cells = <0>;
96 compatible = "wm,wm8750-pll-clock";
97 clocks = <&ref25>;
98 reg = <0x204>;
99 };
100
101 pllc: pllc {
102 #clock-cells = <0>;
103 compatible = "wm,wm8750-pll-clock";
104 clocks = <&ref25>;
105 reg = <0x208>;
106 };
107
108 plld: plld {
109 #clock-cells = <0>;
110 compatible = "wm,wm8750-pll-clock";
111 clocks = <&ref25>;
112 reg = <0x20C>;
113 };
114
115 plle: plle {
116 #clock-cells = <0>;
117 compatible = "wm,wm8750-pll-clock";
118 clocks = <&ref25>;
119 reg = <0x210>;
120 };
121
122 clkarm: arm {
123 #clock-cells = <0>;
124 compatible = "via,vt8500-device-clock";
125 clocks = <&plla>;
126 divisor-reg = <0x300>;
127 };
128
129 clkahb: ahb {
130 #clock-cells = <0>;
131 compatible = "via,vt8500-device-clock";
132 clocks = <&pllb>;
133 divisor-reg = <0x304>;
134 };
135
136 clkapb: apb {
137 #clock-cells = <0>;
138 compatible = "via,vt8500-device-clock";
139 clocks = <&pllb>;
140 divisor-reg = <0x320>;
141 };
142
143 clkddr: ddr {
144 #clock-cells = <0>;
145 compatible = "via,vt8500-device-clock";
146 clocks = <&plld>;
147 divisor-reg = <0x310>;
148 };
149
150 clkuart0: uart0 {
151 #clock-cells = <0>;
152 compatible = "via,vt8500-device-clock";
153 clocks = <&ref24>;
154 enable-reg = <0x254>;
155 enable-bit = <24>;
156 };
157
158 clkuart1: uart1 {
159 #clock-cells = <0>;
160 compatible = "via,vt8500-device-clock";
161 clocks = <&ref24>;
162 enable-reg = <0x254>;
163 enable-bit = <25>;
164 };
165
166 clkuart2: uart2 {
167 #clock-cells = <0>;
168 compatible = "via,vt8500-device-clock";
169 clocks = <&ref24>;
170 enable-reg = <0x254>;
171 enable-bit = <26>;
172 };
173
174 clkuart3: uart3 {
175 #clock-cells = <0>;
176 compatible = "via,vt8500-device-clock";
177 clocks = <&ref24>;
178 enable-reg = <0x254>;
179 enable-bit = <27>;
180 };
181
182 clkuart4: uart4 {
183 #clock-cells = <0>;
184 compatible = "via,vt8500-device-clock";
185 clocks = <&ref24>;
186 enable-reg = <0x254>;
187 enable-bit = <28>;
188 };
189
190 clkuart5: uart5 {
191 #clock-cells = <0>;
192 compatible = "via,vt8500-device-clock";
193 clocks = <&ref24>;
194 enable-reg = <0x254>;
195 enable-bit = <29>;
196 };
197
198 clkpwm: pwm {
199 #clock-cells = <0>;
200 compatible = "via,vt8500-device-clock";
201 clocks = <&pllb>;
202 divisor-reg = <0x350>;
203 enable-reg = <0x250>;
204 enable-bit = <17>;
205 };
206
207 clksdhc: sdhc {
208 #clock-cells = <0>;
209 compatible = "via,vt8500-device-clock";
210 clocks = <&pllb>;
211 divisor-reg = <0x330>;
212 divisor-mask = <0x3f>;
213 enable-reg = <0x250>;
214 enable-bit = <0>;
215 };
216
217 clki2c0: i2c0clk {
218 #clock-cells = <0>;
219 compatible = "via,vt8500-device-clock";
220 clocks = <&pllb>;
221 divisor-reg = <0x3A0>;
222 enable-reg = <0x250>;
223 enable-bit = <8>;
224 };
225
226 clki2c1: i2c1clk {
227 #clock-cells = <0>;
228 compatible = "via,vt8500-device-clock";
229 clocks = <&pllb>;
230 divisor-reg = <0x3A4>;
231 enable-reg = <0x250>;
232 enable-bit = <9>;
233 };
234 };
235 };
236
237 pwm: pwm@d8220000 {
238 #pwm-cells = <3>;
239 compatible = "via,vt8500-pwm";
240 reg = <0xd8220000 0x100>;
241 clocks = <&clkpwm>;
242 };
243
244 timer@d8130100 {
245 compatible = "via,vt8500-timer";
246 reg = <0xd8130100 0x28>;
247 interrupts = <36>;
248 };
249
250 ehci@d8007900 {
251 compatible = "via,vt8500-ehci";
252 reg = <0xd8007900 0x200>;
253 interrupts = <26>;
254 };
255
256 uhci@d8007b00 {
257 compatible = "platform-uhci";
258 reg = <0xd8007b00 0x200>;
259 interrupts = <26>;
260 };
261
262 uhci@d8008d00 {
263 compatible = "platform-uhci";
264 reg = <0xd8008d00 0x200>;
265 interrupts = <26>;
266 };
267
268 uart0: serial@d8200000 {
269 compatible = "via,vt8500-uart";
270 reg = <0xd8200000 0x1040>;
271 interrupts = <32>;
272 clocks = <&clkuart0>;
273 status = "disabled";
274 };
275
276 uart1: serial@d82b0000 {
277 compatible = "via,vt8500-uart";
278 reg = <0xd82b0000 0x1040>;
279 interrupts = <33>;
280 clocks = <&clkuart1>;
281 status = "disabled";
282 };
283
284 uart2: serial@d8210000 {
285 compatible = "via,vt8500-uart";
286 reg = <0xd8210000 0x1040>;
287 interrupts = <47>;
288 clocks = <&clkuart2>;
289 status = "disabled";
290 };
291
292 uart3: serial@d82c0000 {
293 compatible = "via,vt8500-uart";
294 reg = <0xd82c0000 0x1040>;
295 interrupts = <50>;
296 clocks = <&clkuart3>;
297 status = "disabled";
298 };
299
300 uart4: serial@d8370000 {
301 compatible = "via,vt8500-uart";
302 reg = <0xd8370000 0x1040>;
303 interrupts = <30>;
304 clocks = <&clkuart4>;
305 status = "disabled";
306 };
307
308 uart5: serial@d8380000 {
309 compatible = "via,vt8500-uart";
310 reg = <0xd8380000 0x1040>;
311 interrupts = <43>;
312 clocks = <&clkuart5>;
313 status = "disabled";
314 };
315
316 rtc@d8100000 {
317 compatible = "via,vt8500-rtc";
318 reg = <0xd8100000 0x10000>;
319 interrupts = <48>;
320 };
321
322 sdhc@d800a000 {
323 compatible = "wm,wm8505-sdhc";
324 reg = <0xd800a000 0x1000>;
325 interrupts = <20 21>;
326 clocks = <&clksdhc>;
327 bus-width = <4>;
328 sdon-inverted;
329 };
330
331 i2c_0: i2c@d8280000 {
332 compatible = "wm,wm8505-i2c";
333 reg = <0xd8280000 0x1000>;
334 interrupts = <19>;
335 clocks = <&clki2c0>;
336 clock-frequency = <400000>;
337 };
338
339 i2c_1: i2c@d8320000 {
340 compatible = "wm,wm8505-i2c";
341 reg = <0xd8320000 0x1000>;
342 interrupts = <18>;
343 clocks = <&clki2c1>;
344 clock-frequency = <400000>;
345 };
346 };
347};
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
index 32d22532cd6c..90e913fb64be 100644
--- a/arch/arm/boot/dts/wm8850-w70v2.dts
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -41,3 +41,7 @@
41 }; 41 };
42 }; 42 };
43}; 43};
44
45&uart0 {
46 status = "okay";
47};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index fc790d0aee66..d98386dd2882 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -11,6 +11,17 @@
11/ { 11/ {
12 compatible = "wm,wm8850"; 12 compatible = "wm,wm8850";
13 13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a9";
21 reg = <0x0>;
22 };
23 };
24
14 aliases { 25 aliases {
15 serial0 = &uart0; 26 serial0 = &uart0;
16 serial1 = &uart1; 27 serial1 = &uart1;
@@ -72,18 +83,81 @@
72 83
73 plla: plla { 84 plla: plla {
74 #clock-cells = <0>; 85 #clock-cells = <0>;
75 compatible = "wm,wm8750-pll-clock"; 86 compatible = "wm,wm8850-pll-clock";
76 clocks = <&ref25>; 87 clocks = <&ref24>;
77 reg = <0x200>; 88 reg = <0x200>;
78 }; 89 };
79 90
80 pllb: pllb { 91 pllb: pllb {
81 #clock-cells = <0>; 92 #clock-cells = <0>;
82 compatible = "wm,wm8750-pll-clock"; 93 compatible = "wm,wm8850-pll-clock";
83 clocks = <&ref25>; 94 clocks = <&ref24>;
84 reg = <0x204>; 95 reg = <0x204>;
85 }; 96 };
86 97
98 pllc: pllc {
99 #clock-cells = <0>;
100 compatible = "wm,wm8850-pll-clock";
101 clocks = <&ref24>;
102 reg = <0x208>;
103 };
104
105 plld: plld {
106 #clock-cells = <0>;
107 compatible = "wm,wm8850-pll-clock";
108 clocks = <&ref24>;
109 reg = <0x20c>;
110 };
111
112 plle: plle {
113 #clock-cells = <0>;
114 compatible = "wm,wm8850-pll-clock";
115 clocks = <&ref24>;
116 reg = <0x210>;
117 };
118
119 pllf: pllf {
120 #clock-cells = <0>;
121 compatible = "wm,wm8850-pll-clock";
122 clocks = <&ref24>;
123 reg = <0x214>;
124 };
125
126 pllg: pllg {
127 #clock-cells = <0>;
128 compatible = "wm,wm8850-pll-clock";
129 clocks = <&ref24>;
130 reg = <0x218>;
131 };
132
133 clkarm: arm {
134 #clock-cells = <0>;
135 compatible = "via,vt8500-device-clock";
136 clocks = <&plla>;
137 divisor-reg = <0x300>;
138 };
139
140 clkahb: ahb {
141 #clock-cells = <0>;
142 compatible = "via,vt8500-device-clock";
143 clocks = <&pllb>;
144 divisor-reg = <0x304>;
145 };
146
147 clkapb: apb {
148 #clock-cells = <0>;
149 compatible = "via,vt8500-device-clock";
150 clocks = <&pllb>;
151 divisor-reg = <0x320>;
152 };
153
154 clkddr: ddr {
155 #clock-cells = <0>;
156 compatible = "via,vt8500-device-clock";
157 clocks = <&plld>;
158 divisor-reg = <0x310>;
159 };
160
87 clkuart0: uart0 { 161 clkuart0: uart0 {
88 #clock-cells = <0>; 162 #clock-cells = <0>;
89 compatible = "via,vt8500-device-clock"; 163 compatible = "via,vt8500-device-clock";
@@ -178,32 +252,36 @@
178 interrupts = <26>; 252 interrupts = <26>;
179 }; 253 };
180 254
181 uart0: uart@d8200000 { 255 uart0: serial@d8200000 {
182 compatible = "via,vt8500-uart"; 256 compatible = "via,vt8500-uart";
183 reg = <0xd8200000 0x1040>; 257 reg = <0xd8200000 0x1040>;
184 interrupts = <32>; 258 interrupts = <32>;
185 clocks = <&clkuart0>; 259 clocks = <&clkuart0>;
260 status = "disabled";
186 }; 261 };
187 262
188 uart1: uart@d82b0000 { 263 uart1: serial@d82b0000 {
189 compatible = "via,vt8500-uart"; 264 compatible = "via,vt8500-uart";
190 reg = <0xd82b0000 0x1040>; 265 reg = <0xd82b0000 0x1040>;
191 interrupts = <33>; 266 interrupts = <33>;
192 clocks = <&clkuart1>; 267 clocks = <&clkuart1>;
268 status = "disabled";
193 }; 269 };
194 270
195 uart2: uart@d8210000 { 271 uart2: serial@d8210000 {
196 compatible = "via,vt8500-uart"; 272 compatible = "via,vt8500-uart";
197 reg = <0xd8210000 0x1040>; 273 reg = <0xd8210000 0x1040>;
198 interrupts = <47>; 274 interrupts = <47>;
199 clocks = <&clkuart2>; 275 clocks = <&clkuart2>;
276 status = "disabled";
200 }; 277 };
201 278
202 uart3: uart@d82c0000 { 279 uart3: serial@d82c0000 {
203 compatible = "via,vt8500-uart"; 280 compatible = "via,vt8500-uart";
204 reg = <0xd82c0000 0x1040>; 281 reg = <0xd82c0000 0x1040>;
205 interrupts = <50>; 282 interrupts = <50>;
206 clocks = <&clkuart3>; 283 clocks = <&clkuart3>;
284 status = "disabled";
207 }; 285 };
208 286
209 rtc@d8100000 { 287 rtc@d8100000 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 18:39:39 -0500