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authorShawn Guo <shawn.guo@linaro.org>2013-11-04 01:45:46 -0500
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 08:32:25 -0500
commit7ac0f700a6d747c2a8a873e301e82092306173e4 (patch)
treeefa2ea9c8062d3b2b6ba9ca4a34ed4099838aaa3 /arch/arm/boot
parent81d16420c20a061704d67a9309a139a9cbb820c8 (diff)
ARM: dts: imx53: make pinctrl nodes board specific
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts28
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts77
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts164
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts2
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts123
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts119
-rw-r--r--arch/arm/boot/dts/imx53-tqma53.dtsi170
-rw-r--r--arch/arm/boot/dts/imx53.dtsi508
8 files changed, 602 insertions, 589 deletions
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 174f86938c89..bf0a42cda055 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -99,7 +99,7 @@
99 99
100&esdhc1 { 100&esdhc1 {
101 pinctrl-names = "default"; 101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_esdhc1_2>; 102 pinctrl-0 = <&pinctrl_esdhc1>;
103 cd-gpios = <&gpio1 1 0>; 103 cd-gpios = <&gpio1 1 0>;
104 wp-gpios = <&gpio1 9 0>; 104 wp-gpios = <&gpio1 9 0>;
105 status = "okay"; 105 status = "okay";
@@ -109,7 +109,7 @@
109 pinctrl-names = "default"; 109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_hog>; 110 pinctrl-0 = <&pinctrl_hog>;
111 111
112 hog { 112 imx53-ard {
113 pinctrl_hog: hoggrp { 113 pinctrl_hog: hoggrp {
114 fsl,pins = < 114 fsl,pins = <
115 MX53_PAD_GPIO_1__GPIO1_1 0x80000000 115 MX53_PAD_GPIO_1__GPIO1_1 0x80000000
@@ -148,11 +148,33 @@
148 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 148 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
149 >; 149 >;
150 }; 150 };
151
152 pinctrl_esdhc1: esdhc1grp {
153 fsl,pins = <
154 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
155 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
156 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
157 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
158 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
159 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
160 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
161 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
162 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
163 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
164 >;
165 };
166
167 pinctrl_uart1: uart1grp {
168 fsl,pins = <
169 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
170 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
171 >;
172 };
151 }; 173 };
152}; 174};
153 175
154&uart1 { 176&uart1 {
155 pinctrl-names = "default"; 177 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_uart1_2>; 178 pinctrl-0 = <&pinctrl_uart1>;
157 status = "okay"; 179 status = "okay";
158}; 180};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 801fda728ed6..2727a6f593a3 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -34,7 +34,7 @@
34 34
35&esdhc1 { 35&esdhc1 {
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc1_1>; 37 pinctrl-0 = <&pinctrl_esdhc1>;
38 cd-gpios = <&gpio3 13 0>; 38 cd-gpios = <&gpio3 13 0>;
39 wp-gpios = <&gpio3 14 0>; 39 wp-gpios = <&gpio3 14 0>;
40 status = "okay"; 40 status = "okay";
@@ -42,7 +42,7 @@
42 42
43&ecspi1 { 43&ecspi1 {
44 pinctrl-names = "default"; 44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_ecspi1_1>; 45 pinctrl-0 = <&pinctrl_ecspi1>;
46 fsl,spi-num-chipselects = <2>; 46 fsl,spi-num-chipselects = <2>;
47 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 47 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
48 status = "okay"; 48 status = "okay";
@@ -69,7 +69,7 @@
69 69
70&esdhc3 { 70&esdhc3 {
71 pinctrl-names = "default"; 71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_esdhc3_1>; 72 pinctrl-0 = <&pinctrl_esdhc3>;
73 cd-gpios = <&gpio3 11 0>; 73 cd-gpios = <&gpio3 11 0>;
74 wp-gpios = <&gpio3 12 0>; 74 wp-gpios = <&gpio3 12 0>;
75 status = "okay"; 75 status = "okay";
@@ -79,7 +79,7 @@
79 pinctrl-names = "default"; 79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_hog>; 80 pinctrl-0 = <&pinctrl_hog>;
81 81
82 hog { 82 imx53-evk {
83 pinctrl_hog: hoggrp { 83 pinctrl_hog: hoggrp {
84 fsl,pins = < 84 fsl,pins = <
85 MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 85 MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
@@ -92,18 +92,81 @@
92 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 92 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
93 >; 93 >;
94 }; 94 };
95
96 pinctrl_ecspi1: ecspi1grp {
97 fsl,pins = <
98 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
99 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
100 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
101 >;
102 };
103
104 pinctrl_esdhc1: esdhc1grp {
105 fsl,pins = <
106 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
107 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
108 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
109 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
110 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
111 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
112 >;
113 };
114
115 pinctrl_esdhc3: esdhc3grp {
116 fsl,pins = <
117 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
118 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
119 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
120 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
121 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
122 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
123 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
124 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
125 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
126 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
127 >;
128 };
129
130 pinctrl_fec: fecgrp {
131 fsl,pins = <
132 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
133 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
134 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
135 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
136 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
137 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
138 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
139 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
140 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
141 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
142 >;
143 };
144
145 pinctrl_i2c2: i2c2grp {
146 fsl,pins = <
147 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
148 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
149 >;
150 };
151
152 pinctrl_uart1: uart1grp {
153 fsl,pins = <
154 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
155 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
156 >;
157 };
95 }; 158 };
96}; 159};
97 160
98&uart1 { 161&uart1 {
99 pinctrl-names = "default"; 162 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart1_1>; 163 pinctrl-0 = <&pinctrl_uart1>;
101 status = "okay"; 164 status = "okay";
102}; 165};
103 166
104&i2c2 { 167&i2c2 {
105 pinctrl-names = "default"; 168 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c2_1>; 169 pinctrl-0 = <&pinctrl_i2c2>;
107 status = "okay"; 170 status = "okay";
108 171
109 pmic: mc13892@08 { 172 pmic: mc13892@08 {
@@ -119,7 +182,7 @@
119 182
120&fec { 183&fec {
121 pinctrl-names = "default"; 184 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_fec_1>; 185 pinctrl-0 = <&pinctrl_fec>;
123 phy-mode = "rmii"; 186 phy-mode = "rmii";
124 phy-reset-gpios = <&gpio7 6 0>; 187 phy-reset-gpios = <&gpio7 6 0>;
125 status = "okay"; 188 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index 7d304d02ed38..b3133e881118 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -26,7 +26,7 @@
26 crtcs = <&ipu 1>; 26 crtcs = <&ipu 1>;
27 interface-pix-fmt = "bgr666"; 27 interface-pix-fmt = "bgr666";
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp2_1>; 29 pinctrl-0 = <&pinctrl_ipu_disp2>;
30 30
31 display-timings { 31 display-timings {
32 800x480p60 { 32 800x480p60 {
@@ -102,25 +102,25 @@
102 102
103&audmux { 103&audmux {
104 pinctrl-names = "default"; 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_audmux_2>; 105 pinctrl-0 = <&pinctrl_audmux>;
106 status = "okay"; 106 status = "okay";
107}; 107};
108 108
109&can1 { 109&can1 {
110 pinctrl-names = "default"; 110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_can1_3>; 111 pinctrl-0 = <&pinctrl_can1>;
112 status = "okay"; 112 status = "okay";
113}; 113};
114 114
115&can2 { 115&can2 {
116 pinctrl-names = "default"; 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_can2_1>; 117 pinctrl-0 = <&pinctrl_can2>;
118 status = "okay"; 118 status = "okay";
119}; 119};
120 120
121&esdhc1 { 121&esdhc1 {
122 pinctrl-names = "default"; 122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_esdhc1_1>; 123 pinctrl-0 = <&pinctrl_esdhc1>;
124 cd-gpios = <&gpio1 1 0>; 124 cd-gpios = <&gpio1 1 0>;
125 wp-gpios = <&gpio1 9 0>; 125 wp-gpios = <&gpio1 9 0>;
126 status = "okay"; 126 status = "okay";
@@ -128,14 +128,14 @@
128 128
129&fec { 129&fec {
130 pinctrl-names = "default"; 130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_fec_1>; 131 pinctrl-0 = <&pinctrl_fec>;
132 phy-mode = "rmii"; 132 phy-mode = "rmii";
133 status = "okay"; 133 status = "okay";
134}; 134};
135 135
136&i2c1 { 136&i2c1 {
137 pinctrl-names = "default"; 137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c1_2>; 138 pinctrl-0 = <&pinctrl_i2c1>;
139 status = "okay"; 139 status = "okay";
140 140
141 sgtl5000: codec@0a { 141 sgtl5000: codec@0a {
@@ -149,7 +149,7 @@
149 149
150&i2c2 { 150&i2c2 {
151 pinctrl-names = "default"; 151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c2_2>; 152 pinctrl-0 = <&pinctrl_i2c2>;
153 clock-frequency = <400000>; 153 clock-frequency = <400000>;
154 status = "okay"; 154 status = "okay";
155 155
@@ -193,7 +193,7 @@
193 193
194&i2c3 { 194&i2c3 {
195 pinctrl-names = "default"; 195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c3_1>; 196 pinctrl-0 = <&pinctrl_i2c3>;
197 status = "okay"; 197 status = "okay";
198}; 198};
199 199
@@ -201,7 +201,7 @@
201 pinctrl-names = "default"; 201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_hog>; 202 pinctrl-0 = <&pinctrl_hog>;
203 203
204 hog { 204 imx53-m53evk {
205 pinctrl_hog: hoggrp { 205 pinctrl_hog: hoggrp {
206 fsl,pins = < 206 fsl,pins = <
207 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 207 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
@@ -218,12 +218,146 @@
218 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 218 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
219 >; 219 >;
220 }; 220 };
221
222 pinctrl_audmux: audmuxgrp {
223 fsl,pins = <
224 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
225 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
226 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
227 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
228 >;
229 };
230
231 pinctrl_can1: can1grp {
232 fsl,pins = <
233 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
234 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
235 >;
236 };
237
238 pinctrl_can2: can2grp {
239 fsl,pins = <
240 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
241 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
242 >;
243 };
244
245 pinctrl_esdhc1: esdhc1grp {
246 fsl,pins = <
247 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
248 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
249 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
250 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
251 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
252 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
253 >;
254 };
255
256 pinctrl_fec: fecgrp {
257 fsl,pins = <
258 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
259 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
260 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
261 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
262 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
263 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
264 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
265 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
266 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
267 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
268 >;
269 };
270
271 pinctrl_i2c1: i2c1grp {
272 fsl,pins = <
273 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
274 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
275 >;
276 };
277
278 pinctrl_i2c2: i2c2grp {
279 fsl,pins = <
280 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
281 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
282 >;
283 };
284
285 pinctrl_i2c3: i2c3grp {
286 fsl,pins = <
287 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
288 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
289 >;
290 };
291
292 pinctrl_ipu_disp2: ipudisp2grp {
293 fsl,pins = <
294 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
295 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
296 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
297 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
298 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
299 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
300 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
301 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
302 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
303 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
304 >;
305 };
306
307 pinctrl_nand: nandgrp {
308 fsl,pins = <
309 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
310 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
311 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
312 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
313 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
314 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
315 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
316 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
317 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
318 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
319 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
320 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
321 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
322 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
323 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
324 >;
325 };
326
327 pinctrl_pwm1: pwm1grp {
328 fsl,pins = <
329 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
330 >;
331 };
332
333 pinctrl_uart1: uart1grp {
334 fsl,pins = <
335 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
336 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
337 >;
338 };
339
340 pinctrl_uart2: uart2grp {
341 fsl,pins = <
342 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
343 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
344 >;
345 };
346
347 pinctrl_uart3: uart3grp {
348 fsl,pins = <
349 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
350 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
351 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
352 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
353 >;
354 };
221 }; 355 };
222}; 356};
223 357
224&nfc { 358&nfc {
225 pinctrl-names = "default"; 359 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_nand_1>; 360 pinctrl-0 = <&pinctrl_nand>;
227 nand-bus-width = <8>; 361 nand-bus-width = <8>;
228 nand-ecc-mode = "hw"; 362 nand-ecc-mode = "hw";
229 status = "okay"; 363 status = "okay";
@@ -231,7 +365,7 @@
231 365
232&pwm1 { 366&pwm1 {
233 pinctrl-names = "default"; 367 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_pwm1_1>; 368 pinctrl-0 = <&pinctrl_pwm1>;
235 status = "okay"; 369 status = "okay";
236}; 370};
237 371
@@ -242,18 +376,18 @@
242 376
243&uart1 { 377&uart1 {
244 pinctrl-names = "default"; 378 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_uart1_2>; 379 pinctrl-0 = <&pinctrl_uart1>;
246 status = "okay"; 380 status = "okay";
247}; 381};
248 382
249&uart2 { 383&uart2 {
250 pinctrl-names = "default"; 384 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_uart2_1>; 385 pinctrl-0 = <&pinctrl_uart2>;
252 status = "okay"; 386 status = "okay";
253}; 387};
254 388
255&uart3 { 389&uart3 {
256 pinctrl-names = "default"; 390 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_uart3_1>; 391 pinctrl-0 = <&pinctrl_uart3>;
258 status = "okay"; 392 status = "okay";
259}; 393};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index a63090267941..ba95b78e16db 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -148,7 +148,7 @@
148&audmux { 148&audmux {
149 status = "okay"; 149 status = "okay";
150 pinctrl-names = "default"; 150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_audmux_1>; 151 pinctrl-0 = <&pinctrl_audmux>;
152}; 152};
153 153
154&i2c2 { 154&i2c2 {
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 91a5935a4aac..7755836ebf2b 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -26,7 +26,7 @@
26 crtcs = <&ipu 0>; 26 crtcs = <&ipu 0>;
27 interface-pix-fmt = "rgb565"; 27 interface-pix-fmt = "rgb565";
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp0_1>; 29 pinctrl-0 = <&pinctrl_ipu_disp0>;
30 status = "disabled"; 30 status = "disabled";
31 display-timings { 31 display-timings {
32 claawvga { 32 claawvga {
@@ -122,7 +122,7 @@
122 122
123&esdhc1 { 123&esdhc1 {
124 pinctrl-names = "default"; 124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_esdhc1_1>; 125 pinctrl-0 = <&pinctrl_esdhc1>;
126 status = "okay"; 126 status = "okay";
127}; 127};
128 128
@@ -133,7 +133,7 @@
133 133
134&esdhc3 { 134&esdhc3 {
135 pinctrl-names = "default"; 135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_esdhc3_1>; 136 pinctrl-0 = <&pinctrl_esdhc3>;
137 cd-gpios = <&gpio3 11 0>; 137 cd-gpios = <&gpio3 11 0>;
138 wp-gpios = <&gpio3 12 0>; 138 wp-gpios = <&gpio3 12 0>;
139 bus-width = <8>; 139 bus-width = <8>;
@@ -144,7 +144,7 @@
144 pinctrl-names = "default"; 144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_hog>; 145 pinctrl-0 = <&pinctrl_hog>;
146 146
147 hog { 147 imx53-qsb {
148 pinctrl_hog: hoggrp { 148 pinctrl_hog: hoggrp {
149 fsl,pins = < 149 fsl,pins = <
150 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 150 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
@@ -164,19 +164,122 @@
164 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 164 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
165 >; 165 >;
166 }; 166 };
167 };
168 167
168 pinctrl_audmux: audmuxgrp {
169 fsl,pins = <
170 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
171 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
172 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
173 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
174 >;
175 };
176
177 pinctrl_esdhc1: esdhc1grp {
178 fsl,pins = <
179 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
180 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
181 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
182 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
183 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
184 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
185 >;
186 };
187
188 pinctrl_esdhc3: esdhc3grp {
189 fsl,pins = <
190 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
191 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
192 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
193 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
194 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
195 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
196 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
197 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
198 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
199 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
200 >;
201 };
202
203 pinctrl_fec: fecgrp {
204 fsl,pins = <
205 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
206 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
207 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
208 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
209 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
210 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
211 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
212 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
213 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
214 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
215 >;
216 };
217
218 pinctrl_i2c1: i2c1grp {
219 fsl,pins = <
220 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
221 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
222 >;
223 };
224
225 pinctrl_i2c2: i2c2grp {
226 fsl,pins = <
227 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
228 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
229 >;
230 };
231
232 pinctrl_ipu_disp0: ipudisp0grp {
233 fsl,pins = <
234 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
235 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
236 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
237 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
238 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
239 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
240 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
241 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
242 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
243 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
244 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
245 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
246 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
247 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
248 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
249 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
250 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
251 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
252 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
253 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
254 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
255 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
256 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
257 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
258 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
259 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
260 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
261 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
262 >;
263 };
264
265 pinctrl_uart1: uart1grp {
266 fsl,pins = <
267 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
268 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
269 >;
270 };
271 };
169}; 272};
170 273
171&uart1 { 274&uart1 {
172 pinctrl-names = "default"; 275 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_uart1_1>; 276 pinctrl-0 = <&pinctrl_uart1>;
174 status = "okay"; 277 status = "okay";
175}; 278};
176 279
177&i2c2 { 280&i2c2 {
178 pinctrl-names = "default"; 281 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2_1>; 282 pinctrl-0 = <&pinctrl_i2c2>;
180 status = "okay"; 283 status = "okay";
181 284
182 sgtl5000: codec@0a { 285 sgtl5000: codec@0a {
@@ -190,7 +293,7 @@
190 293
191&i2c1 { 294&i2c1 {
192 pinctrl-names = "default"; 295 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c1_1>; 296 pinctrl-0 = <&pinctrl_i2c1>;
194 status = "okay"; 297 status = "okay";
195 298
196 accelerometer: mma8450@1c { 299 accelerometer: mma8450@1c {
@@ -295,13 +398,13 @@
295 398
296&audmux { 399&audmux {
297 pinctrl-names = "default"; 400 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_audmux_1>; 401 pinctrl-0 = <&pinctrl_audmux>;
299 status = "okay"; 402 status = "okay";
300}; 403};
301 404
302&fec { 405&fec {
303 pinctrl-names = "default"; 406 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_fec_1>; 407 pinctrl-0 = <&pinctrl_fec>;
305 phy-mode = "rmii"; 408 phy-mode = "rmii";
306 phy-reset-gpios = <&gpio7 6 0>; 409 phy-reset-gpios = <&gpio7 6 0>;
307 status = "okay"; 410 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index a9b6e10de0a5..5ec1590ff7bc 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -40,7 +40,7 @@
40 40
41&esdhc1 { 41&esdhc1 {
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_esdhc1_1>; 43 pinctrl-0 = <&pinctrl_esdhc1>;
44 cd-gpios = <&gpio3 13 0>; 44 cd-gpios = <&gpio3 13 0>;
45 wp-gpios = <&gpio4 11 0>; 45 wp-gpios = <&gpio4 11 0>;
46 status = "okay"; 46 status = "okay";
@@ -48,21 +48,21 @@
48 48
49&esdhc2 { 49&esdhc2 {
50 pinctrl-names = "default"; 50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_esdhc2_1>; 51 pinctrl-0 = <&pinctrl_esdhc2>;
52 non-removable; 52 non-removable;
53 status = "okay"; 53 status = "okay";
54}; 54};
55 55
56&uart3 { 56&uart3 {
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_uart3_1>; 58 pinctrl-0 = <&pinctrl_uart3>;
59 fsl,uart-has-rtscts; 59 fsl,uart-has-rtscts;
60 status = "okay"; 60 status = "okay";
61}; 61};
62 62
63&ecspi1 { 63&ecspi1 {
64 pinctrl-names = "default"; 64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_ecspi1_1>; 65 pinctrl-0 = <&pinctrl_ecspi1>;
66 fsl,spi-num-chipselects = <2>; 66 fsl,spi-num-chipselects = <2>;
67 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 67 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
68 status = "okay"; 68 status = "okay";
@@ -95,7 +95,7 @@
95 95
96&esdhc3 { 96&esdhc3 {
97 pinctrl-names = "default"; 97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_esdhc3_1>; 98 pinctrl-0 = <&pinctrl_esdhc3>;
99 non-removable; 99 non-removable;
100 status = "okay"; 100 status = "okay";
101}; 101};
@@ -104,7 +104,7 @@
104 pinctrl-names = "default"; 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_hog>; 105 pinctrl-0 = <&pinctrl_hog>;
106 106
107 hog { 107 imx53-smd {
108 pinctrl_hog: hoggrp { 108 pinctrl_hog: hoggrp {
109 fsl,pins = < 109 fsl,pins = <
110 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 110 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
@@ -116,24 +116,121 @@
116 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 116 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
117 >; 117 >;
118 }; 118 };
119
120 pinctrl_ecspi1: ecspi1grp {
121 fsl,pins = <
122 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
123 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
124 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
125 >;
126 };
127
128 pinctrl_esdhc1: esdhc1grp {
129 fsl,pins = <
130 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
131 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
132 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
133 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
134 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
135 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
136 >;
137 };
138
139 pinctrl_esdhc2: esdhc2grp {
140 fsl,pins = <
141 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
142 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
143 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
144 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
145 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
146 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
147 >;
148 };
149
150 pinctrl_esdhc3: esdhc3grp {
151 fsl,pins = <
152 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
153 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
154 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
155 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
156 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
157 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
158 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
159 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
160 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
161 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
162 >;
163 };
164
165 pinctrl_fec: fecgrp {
166 fsl,pins = <
167 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
168 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
169 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
170 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
171 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
172 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
173 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
174 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
175 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
176 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
177 >;
178 };
179
180 pinctrl_i2c1: i2c1grp {
181 fsl,pins = <
182 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
183 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
184 >;
185 };
186
187 pinctrl_i2c2: i2c2grp {
188 fsl,pins = <
189 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
190 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
191 >;
192 };
193
194 pinctrl_uart1: uart1grp {
195 fsl,pins = <
196 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
197 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
198 >;
199 };
200
201 pinctrl_uart2: uart2grp {
202 fsl,pins = <
203 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
204 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
205 >;
206 };
207
208 pinctrl_uart3: uart3grp {
209 fsl,pins = <
210 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
211 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
212 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
213 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
214 >;
215 };
119 }; 216 };
120}; 217};
121 218
122&uart1 { 219&uart1 {
123 pinctrl-names = "default"; 220 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart1_1>; 221 pinctrl-0 = <&pinctrl_uart1>;
125 status = "okay"; 222 status = "okay";
126}; 223};
127 224
128&uart2 { 225&uart2 {
129 pinctrl-names = "default"; 226 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart2_1>; 227 pinctrl-0 = <&pinctrl_uart2>;
131 status = "okay"; 228 status = "okay";
132}; 229};
133 230
134&i2c2 { 231&i2c2 {
135 pinctrl-names = "default"; 232 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c2_1>; 233 pinctrl-0 = <&pinctrl_i2c2>;
137 status = "okay"; 234 status = "okay";
138 235
139 codec: sgtl5000@0a { 236 codec: sgtl5000@0a {
@@ -154,7 +251,7 @@
154 251
155&i2c1 { 252&i2c1 {
156 pinctrl-names = "default"; 253 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c1_1>; 254 pinctrl-0 = <&pinctrl_i2c1>;
158 status = "okay"; 255 status = "okay";
159 256
160 accelerometer: mma8450@1c { 257 accelerometer: mma8450@1c {
@@ -175,7 +272,7 @@
175 272
176&fec { 273&fec {
177 pinctrl-names = "default"; 274 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_fec_1>; 275 pinctrl-0 = <&pinctrl_fec>;
179 phy-mode = "rmii"; 276 phy-mode = "rmii";
180 phy-reset-gpios = <&gpio7 6 0>; 277 phy-reset-gpios = <&gpio7 6 0>;
181 status = "okay"; 278 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index abd72af545bf..718dd158fa76 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -35,8 +35,8 @@
35 35
36&esdhc2 { 36&esdhc2 {
37 pinctrl-names = "default"; 37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc2_1>, 38 pinctrl-0 = <&pinctrl_esdhc2>,
39 <&pinctrl_tqma53_esdhc2_2>; 39 <&pinctrl_esdhc2_cdwp>;
40 vmmc-supply = <&reg_3p3v>; 40 vmmc-supply = <&reg_3p3v>;
41 wp-gpios = <&gpio1 2 0>; 41 wp-gpios = <&gpio1 2 0>;
42 cd-gpios = <&gpio1 4 0>; 42 cd-gpios = <&gpio1 4 0>;
@@ -45,13 +45,13 @@
45 45
46&uart3 { 46&uart3 {
47 pinctrl-names = "default"; 47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart3_2>; 48 pinctrl-0 = <&pinctrl_uart3>;
49 status = "disabled"; 49 status = "disabled";
50}; 50};
51 51
52&ecspi1 { 52&ecspi1 {
53 pinctrl-names = "default"; 53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_ecspi1_1>; 54 pinctrl-0 = <&pinctrl_ecspi1>;
55 fsl,spi-num-chipselects = <4>; 55 fsl,spi-num-chipselects = <4>;
56 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, 56 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
57 <&gpio3 24 0>, <&gpio3 25 0>; 57 <&gpio3 24 0>, <&gpio3 25 0>;
@@ -60,7 +60,7 @@
60 60
61&esdhc3 { /* EMMC */ 61&esdhc3 { /* EMMC */
62 pinctrl-names = "default"; 62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_esdhc3_1>; 63 pinctrl-0 = <&pinctrl_esdhc3>;
64 vmmc-supply = <&reg_3p3v>; 64 vmmc-supply = <&reg_3p3v>;
65 non-removable; 65 non-removable;
66 bus-width = <8>; 66 bus-width = <8>;
@@ -71,27 +71,7 @@
71 pinctrl-names = "default"; 71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_hog>; 72 pinctrl-0 = <&pinctrl_hog>;
73 73
74 esdhc2_2 { 74 imx53-tqma53 {
75 pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
76 fsl,pins = <
77 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
78 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
79 >;
80 };
81 };
82
83 i2s {
84 pinctrl_i2s_1: i2s-grp1 {
85 fsl,pins = <
86 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */
87 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */
88 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
89 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */
90 >;
91 };
92 };
93
94 hog {
95 pinctrl_hog: hoggrp { 75 pinctrl_hog: hoggrp {
96 fsl,pins = < 76 fsl,pins = <
97 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ 77 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
@@ -107,43 +87,165 @@
107 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ 87 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
108 >; 88 >;
109 }; 89 };
90
91 pinctrl_audmux: audmuxgrp {
92 fsl,pins = <
93 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
94 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
95 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
96 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
97 >;
98 };
99
100 pinctrl_can1: can1grp {
101 fsl,pins = <
102 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
103 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
104 >;
105 };
106
107 pinctrl_can2: can2grp {
108 fsl,pins = <
109 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
110 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
111 >;
112 };
113
114 pinctrl_cspi: cspigrp {
115 fsl,pins = <
116 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
117 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
118 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
119 >;
120 };
121
122 pinctrl_ecspi1: ecspi1grp {
123 fsl,pins = <
124 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
125 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
126 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
127 >;
128 };
129
130 pinctrl_esdhc2: esdhc2grp {
131 fsl,pins = <
132 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
133 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
134 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
135 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
136 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
137 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
138 >;
139 };
140
141 pinctrl_esdhc2_cdwp: esdhc2cdwp {
142 fsl,pins = <
143 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
144 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
145 >;
146 };
147
148 pinctrl_esdhc3: esdhc3grp {
149 fsl,pins = <
150 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
151 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
152 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
153 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
154 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
155 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
156 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
157 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
158 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
159 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
160 >;
161 };
162
163 pinctrl_fec: fecgrp {
164 fsl,pins = <
165 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
166 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
167 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
168 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
169 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
170 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
171 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
172 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
173 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
174 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
175 >;
176 };
177
178 pinctrl_i2c2: i2c2grp {
179 fsl,pins = <
180 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
181 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
182 >;
183 };
184
185 pinctrl_i2c3: i2c3grp {
186 fsl,pins = <
187 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
188 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
189 >;
190 };
191
192 pinctrl_uart1: uart1grp {
193 fsl,pins = <
194 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
195 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
196 >;
197 };
198
199 pinctrl_uart2: uart2grp {
200 fsl,pins = <
201 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
202 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
203 >;
204 };
205
206 pinctrl_uart3: uart3grp {
207 fsl,pins = <
208 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
209 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
210 >;
211 };
110 }; 212 };
111}; 213};
112 214
113&uart1 { 215&uart1 {
114 pinctrl-names = "default"; 216 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_uart1_2>; 217 pinctrl-0 = <&pinctrl_uart1>;
116 fsl,uart-has-rtscts; 218 fsl,uart-has-rtscts;
117 status = "disabled"; 219 status = "disabled";
118}; 220};
119 221
120&uart2 { 222&uart2 {
121 pinctrl-names = "default"; 223 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_uart2_1>; 224 pinctrl-0 = <&pinctrl_uart2>;
123 status = "disabled"; 225 status = "disabled";
124}; 226};
125 227
126&can1 { 228&can1 {
127 pinctrl-names = "default"; 229 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_can1_2>; 230 pinctrl-0 = <&pinctrl_can1>;
129 status = "disabled"; 231 status = "disabled";
130}; 232};
131 233
132&can2 { 234&can2 {
133 pinctrl-names = "default"; 235 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_can2_1>; 236 pinctrl-0 = <&pinctrl_can2>;
135 status = "disabled"; 237 status = "disabled";
136}; 238};
137 239
138&i2c3 { 240&i2c3 {
139 pinctrl-names = "default"; 241 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c3_1>; 242 pinctrl-0 = <&pinctrl_i2c3>;
141 status = "disabled"; 243 status = "disabled";
142}; 244};
143 245
144&cspi { 246&cspi {
145 pinctrl-names = "default"; 247 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_cspi_1>; 248 pinctrl-0 = <&pinctrl_cspi>;
147 fsl,spi-num-chipselects = <3>; 249 fsl,spi-num-chipselects = <3>;
148 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, 250 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
149 <&gpio1 21 0>; 251 <&gpio1 21 0>;
@@ -152,7 +254,7 @@
152 254
153&i2c2 { 255&i2c2 {
154 pinctrl-names = "default"; 256 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c2_1>; 257 pinctrl-0 = <&pinctrl_i2c2>;
156 status = "okay"; 258 status = "okay";
157 259
158 pmic: mc34708@8 { 260 pmic: mc34708@8 {
@@ -177,7 +279,7 @@
177 279
178&fec { 280&fec {
179 pinctrl-names = "default"; 281 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_fec_1>; 282 pinctrl-0 = <&pinctrl_fec>;
181 phy-mode = "rmii"; 283 phy-mode = "rmii";
182 status = "disabled"; 284 status = "disabled";
183}; 285};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index dbf253fa799b..7f06203d1606 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -315,514 +315,6 @@
315 iomuxc: iomuxc@53fa8000 { 315 iomuxc: iomuxc@53fa8000 {
316 compatible = "fsl,imx53-iomuxc"; 316 compatible = "fsl,imx53-iomuxc";
317 reg = <0x53fa8000 0x4000>; 317 reg = <0x53fa8000 0x4000>;
318
319 audmux {
320 pinctrl_audmux_1: audmuxgrp-1 {
321 fsl,pins = <
322 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
323 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
324 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
325 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
326 >;
327 };
328
329 pinctrl_audmux_2: audmuxgrp-2 {
330 fsl,pins = <
331 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
332 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
333 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
334 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
335 >;
336 };
337
338 pinctrl_audmux_3: audmuxgrp-3 {
339 fsl,pins = <
340 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
341 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
342 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
343 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
344 >;
345 };
346 };
347
348 fec {
349 pinctrl_fec_1: fecgrp-1 {
350 fsl,pins = <
351 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
352 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
353 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
354 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
355 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
356 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
357 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
358 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
359 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
360 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
361 >;
362 };
363
364 pinctrl_fec_2: fecgrp-2 {
365 fsl,pins = <
366 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
367 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
368 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
369 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
370 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
371 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
372 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
373 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
374 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
375 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
376 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
377 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
378 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
379 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
380 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
381 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
382 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
383 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
384 >;
385 };
386 };
387
388 csi {
389 pinctrl_csi_1: csigrp-1 {
390 fsl,pins = <
391 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
392 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
393 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
394 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
395 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
396 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
397 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
398 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
399 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
400 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
401 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
402 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
403 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
404 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
405 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
406 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
407 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
408 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
409 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
410 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
411 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
412 >;
413 };
414
415 pinctrl_csi_2: csigrp-2 {
416 fsl,pins = <
417 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
418 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
419 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
420 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
421 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
422 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
423 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
424 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
425 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
426 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
427 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
428 >;
429 };
430 };
431
432 cspi {
433 pinctrl_cspi_1: cspigrp-1 {
434 fsl,pins = <
435 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
436 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
437 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
438 >;
439 };
440
441 pinctrl_cspi_2: cspigrp-2 {
442 fsl,pins = <
443 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
444 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
445 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
446 >;
447 };
448 };
449
450 ecspi1 {
451 pinctrl_ecspi1_1: ecspi1grp-1 {
452 fsl,pins = <
453 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
454 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
455 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
456 >;
457 };
458
459 pinctrl_ecspi1_2: ecspi1grp-2 {
460 fsl,pins = <
461 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
462 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
463 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
464 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
465 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
466 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
467 >;
468 };
469 };
470
471 ecspi2 {
472 pinctrl_ecspi2_1: ecspi2grp-1 {
473 fsl,pins = <
474 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
475 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
476 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
477 >;
478 };
479 };
480
481 esdhc1 {
482 pinctrl_esdhc1_1: esdhc1grp-1 {
483 fsl,pins = <
484 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
485 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
486 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
487 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
488 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
489 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
490 >;
491 };
492
493 pinctrl_esdhc1_2: esdhc1grp-2 {
494 fsl,pins = <
495 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
496 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
497 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
498 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
499 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
500 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
501 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
502 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
503 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
504 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
505 >;
506 };
507 };
508
509 esdhc2 {
510 pinctrl_esdhc2_1: esdhc2grp-1 {
511 fsl,pins = <
512 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
513 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
514 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
515 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
516 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
517 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
518 >;
519 };
520 };
521
522 esdhc3 {
523 pinctrl_esdhc3_1: esdhc3grp-1 {
524 fsl,pins = <
525 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
526 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
527 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
528 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
529 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
530 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
531 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
532 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
533 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
534 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
535 >;
536 };
537 };
538
539 can1 {
540 pinctrl_can1_1: can1grp-1 {
541 fsl,pins = <
542 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
543 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
544 >;
545 };
546
547 pinctrl_can1_2: can1grp-2 {
548 fsl,pins = <
549 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
550 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
551 >;
552 };
553
554 pinctrl_can1_3: can1grp-3 {
555 fsl,pins = <
556 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
557 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
558 >;
559 };
560 };
561
562 can2 {
563 pinctrl_can2_1: can2grp-1 {
564 fsl,pins = <
565 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
566 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
567 >;
568 };
569 };
570
571 i2c1 {
572 pinctrl_i2c1_1: i2c1grp-1 {
573 fsl,pins = <
574 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
575 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
576 >;
577 };
578
579 pinctrl_i2c1_2: i2c1grp-2 {
580 fsl,pins = <
581 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
582 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
583 >;
584 };
585 };
586
587 i2c2 {
588 pinctrl_i2c2_1: i2c2grp-1 {
589 fsl,pins = <
590 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
591 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
592 >;
593 };
594
595 pinctrl_i2c2_2: i2c2grp-2 {
596 fsl,pins = <
597 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
598 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
599 >;
600 };
601 };
602
603 i2c3 {
604 pinctrl_i2c3_1: i2c3grp-1 {
605 fsl,pins = <
606 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
607 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
608 >;
609 };
610 };
611
612 ipu_disp0 {
613 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
614 fsl,pins = <
615 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
616 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
617 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
618 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
619 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
620 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
621 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
622 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
623 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
624 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
625 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
626 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
627 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
628 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
629 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
630 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
631 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
632 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
633 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
634 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
635 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
636 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
637 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
638 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
639 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
640 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
641 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
642 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
643 >;
644 };
645 };
646
647 ipu_disp1 {
648 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
649 fsl,pins = <
650 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
651 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
652 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
653 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
654 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
655 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
656 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
657 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
658 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
659 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
660 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
661 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
662 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
663 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
664 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
665 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
666 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
667 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
668 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
669 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
670 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
671 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
672 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
673 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
674 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
675 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
676 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
677 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
678 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
679 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
680 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
681 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
682 >;
683 };
684 };
685
686 ipu_disp2 {
687 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
688 fsl,pins = <
689 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
690 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
691 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
692 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
693 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
694 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
695 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
696 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
697 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
698 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
699 >;
700 };
701 };
702
703 nand {
704 pinctrl_nand_1: nandgrp-1 {
705 fsl,pins = <
706 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
707 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
708 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
709 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
710 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
711 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
712 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
713 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
714 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
715 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
716 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
717 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
718 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
719 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
720 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
721 >;
722 };
723 };
724
725 owire {
726 pinctrl_owire_1: owiregrp-1 {
727 fsl,pins = <
728 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
729 >;
730 };
731 };
732
733 pwm1 {
734 pinctrl_pwm1_1: pwm1grp-1 {
735 fsl,pins = <
736 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
737 >;
738 };
739 };
740
741 pwm2 {
742 pinctrl_pwm2_1: pwm2grp-1 {
743 fsl,pins = <
744 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
745 >;
746 };
747 };
748
749 uart1 {
750 pinctrl_uart1_1: uart1grp-1 {
751 fsl,pins = <
752 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
753 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
754 >;
755 };
756
757 pinctrl_uart1_2: uart1grp-2 {
758 fsl,pins = <
759 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
760 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
761 >;
762 };
763
764 pinctrl_uart1_3: uart1grp-3 {
765 fsl,pins = <
766 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
767 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
768 >;
769 };
770 };
771
772 uart2 {
773 pinctrl_uart2_1: uart2grp-1 {
774 fsl,pins = <
775 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
776 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
777 >;
778 };
779
780 pinctrl_uart2_2: uart2grp-2 {
781 fsl,pins = <
782 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
783 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
784 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
785 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
786 >;
787 };
788 };
789
790 uart3 {
791 pinctrl_uart3_1: uart3grp-1 {
792 fsl,pins = <
793 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
794 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
795 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
796 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
797 >;
798 };
799
800 pinctrl_uart3_2: uart3grp-2 {
801 fsl,pins = <
802 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
803 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
804 >;
805 };
806
807 };
808
809 uart4 {
810 pinctrl_uart4_1: uart4grp-1 {
811 fsl,pins = <
812 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
813 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
814 >;
815 };
816 };
817
818 uart5 {
819 pinctrl_uart5_1: uart5grp-1 {
820 fsl,pins = <
821 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
822 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
823 >;
824 };
825 };
826 }; 318 };
827 319
828 gpr: iomuxc-gpr@53fa8000 { 320 gpr: iomuxc-gpr@53fa8000 {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 20:31:36 -0400