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authorOlof Johansson <olof@lixom.net>2013-02-05 16:19:11 -0500
committerOlof Johansson <olof@lixom.net>2013-02-05 16:19:11 -0500
commit5b22c33e8e52ea0e2530037da1f97e88c0b42214 (patch)
tree546f1e21ea6764b798ee017a470b69a033a62838 /arch/arm/boot
parent0b6ad80abb1ad1584347e5ec5c5739ebc540a1a7 (diff)
parent3fbf07d80b40f73c304624179381f9038bd03b74 (diff)
Merge tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From Stephen Warren: ARM: tegra: device tree updates Numerous updates to the various Tegra device trees are made: * Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris carrier boards. * Enablement of the HDMI connector on most boards. * Enablement of the keyboard controller on a few boards. * Addition of the AC'97 controller to Tegra20. * Addition of a GPIO poweroff node for TrimSlice. * Changes to support the new "high speed UART" (DMA-capable) driver for Tegra serial ports, and enablement for Cardhu's UART C. * A few cleanups, such as compatible flag fixes, node renames, node ordering fixes, commonizing properties into SoC .dtsi files, etc.. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-t114. * tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (22 commits) ARM: dt: tegra30: Rename "smmu" to "iommu" ARM: dt: tegra20: Rename "gart" to "iommu" ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM ARM: tegra: Add Colibri T20 512MB COM device tree ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi ARM: tegra: harmony: enable keyboard in DT ARM: tegra: whistler: enable keyboard in DT ARM: tegra: cardhu: register UARTC ARM: tegra: seaboard: enable keyboard in DT ARM: tegra: add DT entry for KBC controller ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT ASoC: tegra: add ac97 host controller to device tree ARM: DT: tegra: Add Tegra30 Beaver board support ARM: DT: tegra: Add board level compatible properties ARM: tegra: paz00: enable HDMI port ARM: tegra: ventana: enable HDMI port ARM: tegra: seaboard: enable HDMI port ARM: tegra: trimslice: add gpio-poweroff node to DT ARM: DT: tegra: Unify the description of Tegra20 boards ...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi491
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts120
-rw-r--r--arch/arm/boot/dts/tegra20-iris-512.dts89
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts22
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts158
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi1
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts11
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts23
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts15
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi72
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts373
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi66
14 files changed, 1404 insertions, 54 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ca683a66b498..b1f2ab9cda6e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
136dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \ 136dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
137 sun5i-a13-olinuxino.dtb 137 sun5i-a13-olinuxino.dtb
138dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 138dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
139 tegra20-iris-512.dtb \
139 tegra20-medcom-wide.dtb \ 140 tegra20-medcom-wide.dtb \
140 tegra20-paz00.dtb \ 141 tegra20-paz00.dtb \
141 tegra20-plutux.dtb \ 142 tegra20-plutux.dtb \
@@ -144,6 +145,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
144 tegra20-trimslice.dtb \ 145 tegra20-trimslice.dtb \
145 tegra20-ventana.dtb \ 146 tegra20-ventana.dtb \
146 tegra20-whistler.dtb \ 147 tegra20-whistler.dtb \
148 tegra30-beaver.dtb \
147 tegra30-cardhu-a02.dtb \ 149 tegra30-cardhu-a02.dtb \
148 tegra30-cardhu-a04.dtb \ 150 tegra30-cardhu-a04.dtb \
149 tegra114-dalmore.dtb \ 151 tegra114-dalmore.dtb \
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 000000000000..444162090042
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,491 @@
1/include/ "tegra20.dtsi"
2
3/ {
4 model = "Toradex Colibri T20 512MB";
5 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
11 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&i2c_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18 };
19 };
20
21 pinmux {
22 pinctrl-names = "default";
23 pinctrl-0 = <&state_default>;
24
25 state_default: pinmux {
26 audio_refclk {
27 nvidia,pins = "cdev1";
28 nvidia,function = "plla_out";
29 nvidia,pull = <0>;
30 nvidia,tristate = <0>;
31 };
32 crt {
33 nvidia,pins = "crtp";
34 nvidia,function = "crt";
35 nvidia,pull = <0>;
36 nvidia,tristate = <1>;
37 };
38 dap3 {
39 nvidia,pins = "dap3";
40 nvidia,function = "dap3";
41 nvidia,pull = <0>;
42 nvidia,tristate = <0>;
43 };
44 displaya {
45 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
46 "ld4", "ld5", "ld6", "ld7", "ld8",
47 "ld9", "ld10", "ld11", "ld12", "ld13",
48 "ld14", "ld15", "ld16", "ld17",
49 "lhs", "lpw0", "lpw2", "lsc0",
50 "lsc1", "lsck", "lsda", "lspi", "lvs";
51 nvidia,function = "displaya";
52 nvidia,tristate = <1>;
53 };
54 gpio_dte {
55 nvidia,pins = "dte";
56 nvidia,function = "rsvd1";
57 nvidia,pull = <0>;
58 nvidia,tristate = <0>;
59 };
60 gpio_gmi {
61 nvidia,pins = "ata", "atc", "atd", "ate",
62 "dap1", "dap2", "dap4", "gpu", "irrx",
63 "irtx", "spia", "spib", "spic";
64 nvidia,function = "gmi";
65 nvidia,pull = <0>;
66 nvidia,tristate = <0>;
67 };
68 gpio_pta {
69 nvidia,pins = "pta";
70 nvidia,function = "rsvd4";
71 nvidia,pull = <0>;
72 nvidia,tristate = <0>;
73 };
74 gpio_uac {
75 nvidia,pins = "uac";
76 nvidia,function = "rsvd2";
77 nvidia,pull = <0>;
78 nvidia,tristate = <0>;
79 };
80 hdint {
81 nvidia,pins = "hdint";
82 nvidia,function = "hdmi";
83 nvidia,tristate = <1>;
84 };
85 i2c1 {
86 nvidia,pins = "rm";
87 nvidia,function = "i2c1";
88 nvidia,pull = <0>;
89 nvidia,tristate = <1>;
90 };
91 i2c3 {
92 nvidia,pins = "dtf";
93 nvidia,function = "i2c3";
94 nvidia,pull = <0>;
95 nvidia,tristate = <1>;
96 };
97 i2cddc {
98 nvidia,pins = "ddc";
99 nvidia,function = "i2c2";
100 nvidia,pull = <2>;
101 nvidia,tristate = <1>;
102 };
103 i2cp {
104 nvidia,pins = "i2cp";
105 nvidia,function = "i2cp";
106 nvidia,pull = <0>;
107 nvidia,tristate = <0>;
108 };
109 irda {
110 nvidia,pins = "uad";
111 nvidia,function = "irda";
112 nvidia,pull = <0>;
113 nvidia,tristate = <1>;
114 };
115 nand {
116 nvidia,pins = "kbca", "kbcc", "kbcd",
117 "kbce", "kbcf";
118 nvidia,function = "nand";
119 nvidia,pull = <0>;
120 nvidia,tristate = <0>;
121 };
122 owc {
123 nvidia,pins = "owc";
124 nvidia,function = "owr";
125 nvidia,pull = <0>;
126 nvidia,tristate = <1>;
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 nvidia,tristate = <0>;
132 };
133 pwm {
134 nvidia,pins = "sdb", "sdc", "sdd";
135 nvidia,function = "pwm";
136 nvidia,tristate = <1>;
137 };
138 sdio4 {
139 nvidia,pins = "atb", "gma", "gme";
140 nvidia,function = "sdio4";
141 nvidia,pull = <0>;
142 nvidia,tristate = <1>;
143 };
144 spi1 {
145 nvidia,pins = "spid", "spie", "spif";
146 nvidia,function = "spi1";
147 nvidia,pull = <0>;
148 nvidia,tristate = <1>;
149 };
150 spi4 {
151 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
152 nvidia,function = "spi4";
153 nvidia,pull = <0>;
154 nvidia,tristate = <1>;
155 };
156 uarta {
157 nvidia,pins = "sdio1";
158 nvidia,function = "uarta";
159 nvidia,pull = <0>;
160 nvidia,tristate = <1>;
161 };
162 uartd {
163 nvidia,pins = "gmc";
164 nvidia,function = "uartd";
165 nvidia,pull = <0>;
166 nvidia,tristate = <1>;
167 };
168 ulpi {
169 nvidia,pins = "uaa", "uab", "uda";
170 nvidia,function = "ulpi";
171 nvidia,pull = <0>;
172 nvidia,tristate = <0>;
173 };
174 ulpi_refclk {
175 nvidia,pins = "cdev2";
176 nvidia,function = "pllp_out4";
177 nvidia,pull = <0>;
178 nvidia,tristate = <0>;
179 };
180 usb_gpio {
181 nvidia,pins = "spig", "spih";
182 nvidia,function = "spi2_alt";
183 nvidia,pull = <0>;
184 nvidia,tristate = <0>;
185 };
186 vi {
187 nvidia,pins = "dta", "dtb", "dtc", "dtd";
188 nvidia,function = "vi";
189 nvidia,pull = <0>;
190 nvidia,tristate = <1>;
191 };
192 vi_sc {
193 nvidia,pins = "csus";
194 nvidia,function = "vi_sensor_clk";
195 nvidia,pull = <0>;
196 nvidia,tristate = <1>;
197 };
198 };
199 };
200
201 i2c@7000c000 {
202 clock-frequency = <400000>;
203 };
204
205 i2c_ddc: i2c@7000c400 {
206 clock-frequency = <100000>;
207 };
208
209 i2c@7000c500 {
210 clock-frequency = <400000>;
211 };
212
213 i2c@7000d000 {
214 status = "okay";
215 clock-frequency = <400000>;
216
217 pmic: tps6586x@34 {
218 compatible = "ti,tps6586x";
219 reg = <0x34>;
220 interrupts = <0 86 0x4>;
221
222 ti,system-power-controller;
223
224 #gpio-cells = <2>;
225 gpio-controller;
226
227 sys-supply = <&vdd_5v0_reg>;
228 vin-sm0-supply = <&sys_reg>;
229 vin-sm1-supply = <&sys_reg>;
230 vin-sm2-supply = <&sys_reg>;
231 vinldo01-supply = <&sm2_reg>;
232 vinldo23-supply = <&sm2_reg>;
233 vinldo4-supply = <&sm2_reg>;
234 vinldo678-supply = <&sm2_reg>;
235 vinldo9-supply = <&sm2_reg>;
236
237 regulators {
238 #address-cells = <1>;
239 #size-cells = <0>;
240
241 sys_reg: regulator@0 {
242 reg = <0>;
243 regulator-compatible = "sys";
244 regulator-name = "vdd_sys";
245 regulator-always-on;
246 };
247
248 regulator@1 {
249 reg = <1>;
250 regulator-compatible = "sm0";
251 regulator-name = "vdd_sm0,vdd_core";
252 regulator-min-microvolt = <1275000>;
253 regulator-max-microvolt = <1275000>;
254 regulator-always-on;
255 };
256
257 regulator@2 {
258 reg = <2>;
259 regulator-compatible = "sm1";
260 regulator-name = "vdd_sm1,vdd_cpu";
261 regulator-min-microvolt = <1100000>;
262 regulator-max-microvolt = <1100000>;
263 regulator-always-on;
264 };
265
266 sm2_reg: regulator@3 {
267 reg = <3>;
268 regulator-compatible = "sm2";
269 regulator-name = "vdd_sm2,vin_ldo*";
270 regulator-min-microvolt = <3700000>;
271 regulator-max-microvolt = <3700000>;
272 regulator-always-on;
273 };
274
275 /* LDO0 is not connected to anything */
276
277 regulator@5 {
278 reg = <5>;
279 regulator-compatible = "ldo1";
280 regulator-name = "vdd_ldo1,avdd_pll*";
281 regulator-min-microvolt = <1100000>;
282 regulator-max-microvolt = <1100000>;
283 regulator-always-on;
284 };
285
286 regulator@6 {
287 reg = <6>;
288 regulator-compatible = "ldo2";
289 regulator-name = "vdd_ldo2,vdd_rtc";
290 regulator-min-microvolt = <1200000>;
291 regulator-max-microvolt = <1200000>;
292 };
293
294 /* LDO3 is not connected to anything */
295
296 regulator@8 {
297 reg = <8>;
298 regulator-compatible = "ldo4";
299 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
302 regulator-always-on;
303 };
304
305 ldo5_reg: regulator@9 {
306 reg = <9>;
307 regulator-compatible = "ldo5";
308 regulator-name = "vdd_ldo5,vdd_fuse";
309 regulator-min-microvolt = <3300000>;
310 regulator-max-microvolt = <3300000>;
311 regulator-always-on;
312 };
313
314 regulator@10 {
315 reg = <10>;
316 regulator-compatible = "ldo6";
317 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <1800000>;
320 };
321
322 hdmi_vdd_reg: regulator@11 {
323 reg = <11>;
324 regulator-compatible = "ldo7";
325 regulator-name = "vdd_ldo7,avdd_hdmi";
326 regulator-min-microvolt = <3300000>;
327 regulator-max-microvolt = <3300000>;
328 };
329
330 hdmi_pll_reg: regulator@12 {
331 reg = <12>;
332 regulator-compatible = "ldo8";
333 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 };
337
338 regulator@13 {
339 reg = <13>;
340 regulator-compatible = "ldo9";
341 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
342 regulator-min-microvolt = <2850000>;
343 regulator-max-microvolt = <2850000>;
344 regulator-always-on;
345 };
346
347 regulator@14 {
348 reg = <14>;
349 regulator-compatible = "ldo_rtc";
350 regulator-name = "vdd_rtc_out,vdd_cell";
351 regulator-min-microvolt = <3300000>;
352 regulator-max-microvolt = <3300000>;
353 regulator-always-on;
354 };
355 };
356 };
357
358 temperature-sensor@4c {
359 compatible = "national,lm95245";
360 reg = <0x4c>;
361 };
362 };
363
364 memory-controller@7000f400 {
365 emc-table@83250 {
366 reg = <83250>;
367 compatible = "nvidia,tegra20-emc-table";
368 clock-frequency = <83250>;
369 nvidia,emc-registers = <0x00000005 0x00000011
370 0x00000004 0x00000002 0x00000004 0x00000004
371 0x00000001 0x0000000a 0x00000002 0x00000002
372 0x00000001 0x00000001 0x00000003 0x00000004
373 0x00000003 0x00000009 0x0000000c 0x0000025f
374 0x00000000 0x00000003 0x00000003 0x00000002
375 0x00000002 0x00000001 0x00000008 0x000000c8
376 0x00000003 0x00000005 0x00000003 0x0000000c
377 0x00000002 0x00000000 0x00000000 0x00000002
378 0x00000000 0x00000000 0x00000083 0x00520006
379 0x00000010 0x00000008 0x00000000 0x00000000
380 0x00000000 0x00000000 0x00000000 0x00000000>;
381 };
382 emc-table@133200 {
383 reg = <133200>;
384 compatible = "nvidia,tegra20-emc-table";
385 clock-frequency = <133200>;
386 nvidia,emc-registers = <0x00000008 0x00000019
387 0x00000006 0x00000002 0x00000004 0x00000004
388 0x00000001 0x0000000a 0x00000002 0x00000002
389 0x00000002 0x00000001 0x00000003 0x00000004
390 0x00000003 0x00000009 0x0000000c 0x0000039f
391 0x00000000 0x00000003 0x00000003 0x00000002
392 0x00000002 0x00000001 0x00000008 0x000000c8
393 0x00000003 0x00000007 0x00000003 0x0000000c
394 0x00000002 0x00000000 0x00000000 0x00000002
395 0x00000000 0x00000000 0x00000083 0x00510006
396 0x00000010 0x00000008 0x00000000 0x00000000
397 0x00000000 0x00000000 0x00000000 0x00000000>;
398 };
399 emc-table@166500 {
400 reg = <166500>;
401 compatible = "nvidia,tegra20-emc-table";
402 clock-frequency = <166500>;
403 nvidia,emc-registers = <0x0000000a 0x00000021
404 0x00000008 0x00000003 0x00000004 0x00000004
405 0x00000002 0x0000000a 0x00000003 0x00000003
406 0x00000002 0x00000001 0x00000003 0x00000004
407 0x00000003 0x00000009 0x0000000c 0x000004df
408 0x00000000 0x00000003 0x00000003 0x00000003
409 0x00000003 0x00000001 0x00000009 0x000000c8
410 0x00000003 0x00000009 0x00000004 0x0000000c
411 0x00000002 0x00000000 0x00000000 0x00000002
412 0x00000000 0x00000000 0x00000083 0x004f0006
413 0x00000010 0x00000008 0x00000000 0x00000000
414 0x00000000 0x00000000 0x00000000 0x00000000>;
415 };
416 emc-table@333000 {
417 reg = <333000>;
418 compatible = "nvidia,tegra20-emc-table";
419 clock-frequency = <333000>;
420 nvidia,emc-registers = <0x00000014 0x00000041
421 0x0000000f 0x00000005 0x00000004 0x00000005
422 0x00000003 0x0000000a 0x00000005 0x00000005
423 0x00000004 0x00000001 0x00000003 0x00000004
424 0x00000003 0x00000009 0x0000000c 0x000009ff
425 0x00000000 0x00000003 0x00000003 0x00000005
426 0x00000005 0x00000001 0x0000000e 0x000000c8
427 0x00000003 0x00000011 0x00000006 0x0000000c
428 0x00000002 0x00000000 0x00000000 0x00000002
429 0x00000000 0x00000000 0x00000083 0x00380006
430 0x00000010 0x00000008 0x00000000 0x00000000
431 0x00000000 0x00000000 0x00000000 0x00000000>;
432 };
433 };
434
435 ac97: ac97 {
436 status = "okay";
437 nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
438 nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
439 };
440
441 usb@c5004000 {
442 status = "okay";
443 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
444 };
445
446 sdhci@c8000600 {
447 cd-gpios = <&gpio 23 0>; /* gpio PC7 */
448 };
449
450 sound {
451 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
452 "nvidia,tegra-audio-wm9712";
453 nvidia,model = "Colibri T20 AC97 Audio";
454
455 nvidia,audio-routing =
456 "Headphone", "HPOUTL",
457 "Headphone", "HPOUTR",
458 "LineIn", "LINEINL",
459 "LineIn", "LINEINR",
460 "Mic", "MIC1";
461
462 nvidia,ac97-controller = <&ac97>;
463 };
464
465 regulators {
466 compatible = "simple-bus";
467 #address-cells = <1>;
468 #size-cells = <0>;
469
470 vdd_5v0_reg: regulator@100 {
471 compatible = "regulator-fixed";
472 reg = <100>;
473 regulator-name = "vdd_5v0";
474 regulator-min-microvolt = <5000000>;
475 regulator-max-microvolt = <5000000>;
476 regulator-always-on;
477 };
478
479 regulator@101 {
480 compatible = "regulator-fixed";
481 reg = <101>;
482 regulator-name = "internal_usb";
483 regulator-min-microvolt = <5000000>;
484 regulator-max-microvolt = <5000000>;
485 enable-active-high;
486 regulator-boot-on;
487 regulator-always-on;
488 gpio = <&gpio 217 0>;
489 };
490 };
491};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 2b4169702c8d..61d027f03617 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -3,7 +3,7 @@
3/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra2 Harmony evaluation board"; 6 model = "NVIDIA Tegra20 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20"; 7 compatible = "nvidia,harmony", "nvidia,tegra20";
8 8
9 memory { 9 memory {
@@ -252,7 +252,6 @@
252 252
253 serial@70006300 { 253 serial@70006300 {
254 status = "okay"; 254 status = "okay";
255 clock-frequency = <216000000>;
256 }; 255 };
257 256
258 i2c@7000c000 { 257 i2c@7000c000 {
@@ -452,6 +451,123 @@
452 bus-width = <8>; 451 bus-width = <8>;
453 }; 452 };
454 453
454 kbc {
455 status = "okay";
456 nvidia,debounce-delay-ms = <2>;
457 nvidia,repeat-delay-ms = <160>;
458 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
459 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
460 linux,keymap = <0x00020011 /* KEY_W */
461 0x0003001F /* KEY_S */
462 0x0004001E /* KEY_A */
463 0x0005002C /* KEY_Z */
464 0x000701D0 /* KEY_FN */
465 0x0107008B /* KEY_MENU */
466 0x02060038 /* KEY_LEFTALT */
467 0x02070064 /* KEY_RIGHTALT */
468 0x03000006 /* KEY_5 */
469 0x03010005 /* KEY_4 */
470 0x03020013 /* KEY_R */
471 0x03030012 /* KEY_E */
472 0x03040021 /* KEY_F */
473 0x03050020 /* KEY_D */
474 0x0306002D /* KEY_X */
475 0x04000008 /* KEY_7 */
476 0x04010007 /* KEY_6 */
477 0x04020014 /* KEY_T */
478 0x04030023 /* KEY_H */
479 0x04040022 /* KEY_G */
480 0x0405002F /* KEY_V */
481 0x0406002E /* KEY_C */
482 0x04070039 /* KEY_SPACE */
483 0x0500000A /* KEY_9 */
484 0x05010009 /* KEY_8 */
485 0x05020016 /* KEY_U */
486 0x05030015 /* KEY_Y */
487 0x05040024 /* KEY_J */
488 0x05050031 /* KEY_N */
489 0x05060030 /* KEY_B */
490 0x0507002B /* KEY_BACKSLASH */
491 0x0600000C /* KEY_MINUS */
492 0x0601000B /* KEY_0 */
493 0x06020018 /* KEY_O */
494 0x06030017 /* KEY_I */
495 0x06040026 /* KEY_L */
496 0x06050025 /* KEY_K */
497 0x06060033 /* KEY_COMMA */
498 0x06070032 /* KEY_M */
499 0x0701000D /* KEY_EQUAL */
500 0x0702001B /* KEY_RIGHTBRACE */
501 0x0703001C /* KEY_ENTER */
502 0x0707008B /* KEY_MENU */
503 0x0804002A /* KEY_LEFTSHIFT */
504 0x08050036 /* KEY_RIGHTSHIFT */
505 0x0905001D /* KEY_LEFTCTRL */
506 0x09070061 /* KEY_RIGHTCTRL */
507 0x0B00001A /* KEY_LEFTBRACE */
508 0x0B010019 /* KEY_P */
509 0x0B020028 /* KEY_APOSTROPHE */
510 0x0B030027 /* KEY_SEMICOLON */
511 0x0B040035 /* KEY_SLASH */
512 0x0B050034 /* KEY_DOT */
513 0x0C000044 /* KEY_F10 */
514 0x0C010043 /* KEY_F9 */
515 0x0C02000E /* KEY_BACKSPACE */
516 0x0C030004 /* KEY_3 */
517 0x0C040003 /* KEY_2 */
518 0x0C050067 /* KEY_UP */
519 0x0C0600D2 /* KEY_PRINT */
520 0x0C070077 /* KEY_PAUSE */
521 0x0D00006E /* KEY_INSERT */
522 0x0D01006F /* KEY_DELETE */
523 0x0D030068 /* KEY_PAGEUP */
524 0x0D04006D /* KEY_PAGEDOWN */
525 0x0D05006A /* KEY_RIGHT */
526 0x0D06006C /* KEY_DOWN */
527 0x0D070069 /* KEY_LEFT */
528 0x0E000057 /* KEY_F11 */
529 0x0E010058 /* KEY_F12 */
530 0x0E020042 /* KEY_F8 */
531 0x0E030010 /* KEY_Q */
532 0x0E04003E /* KEY_F4 */
533 0x0E05003D /* KEY_F3 */
534 0x0E060002 /* KEY_1 */
535 0x0E070041 /* KEY_F7 */
536 0x0F000001 /* KEY_ESC */
537 0x0F010029 /* KEY_GRAVE */
538 0x0F02003F /* KEY_F5 */
539 0x0F03000F /* KEY_TAB */
540 0x0F04003B /* KEY_F1 */
541 0x0F05003C /* KEY_F2 */
542 0x0F06003A /* KEY_CAPSLOCK */
543 0x0F070040 /* KEY_F6 */
544 0x14000047 /* KEY_KP7 */
545 0x15000049 /* KEY_KP9 */
546 0x15010048 /* KEY_KP8 */
547 0x1502004B /* KEY_KP4 */
548 0x1504004F /* KEY_KP1 */
549 0x1601004E /* KEY_KPSLASH */
550 0x1602004D /* KEY_KP6 */
551 0x1603004C /* KEY_KP5 */
552 0x16040051 /* KEY_KP3 */
553 0x16050050 /* KEY_KP2 */
554 0x16070052 /* KEY_KP0 */
555 0x1B010037 /* KEY_KPASTERISK */
556 0x1B03004A /* KEY_KPMINUS */
557 0x1B04004E /* KEY_KPPLUS */
558 0x1B050053 /* KEY_KPDOT */
559 0x1C050073 /* KEY_VOLUMEUP */
560 0x1D030066 /* KEY_HOME */
561 0x1D04006B /* KEY_END */
562 0x1D0500E1 /* KEY_BRIGHTNESSUP */
563 0x1D060072 /* KEY_VOLUMEDOWN */
564 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
565 0x1E000045 /* KEY_NUMLOCK */
566 0x1E010046 /* KEY_SCROLLLOCK */
567 0x1E020071 /* KEY_MUTE */
568 0x1F0400D6>; /* KEY_QUESTION */
569 };
570
455 regulators { 571 regulators {
456 compatible = "simple-bus"; 572 compatible = "simple-bus";
457 #address-cells = <1>; 573 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
new file mode 100644
index 000000000000..52f1103907d7
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -0,0 +1,89 @@
1/dts-v1/;
2
3/include/ "tegra20-colibri-512.dtsi"
4
5/ {
6 model = "Toradex Colibri T20 512MB on Iris";
7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
8
9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
15 pinmux {
16 state_default: pinmux {
17 hdint {
18 nvidia,tristate = <0>;
19 };
20
21 i2cddc {
22 nvidia,tristate = <0>;
23 };
24
25 sdio4 {
26 nvidia,tristate = <0>;
27 };
28
29 uarta {
30 nvidia,tristate = <0>;
31 };
32
33 uartd {
34 nvidia,tristate = <0>;
35 };
36 };
37 };
38
39 usb@c5000000 {
40 status = "okay";
41 dr_mode = "otg";
42 };
43
44 usb@c5008000 {
45 status = "okay";
46 };
47
48 serial@70006000 {
49 status = "okay";
50 };
51
52 serial@70006300 {
53 status = "okay";
54 };
55
56 i2c_ddc: i2c@7000c400 {
57 status = "okay";
58 };
59
60 sdhci@c8000600 {
61 status = "okay";
62 bus-width = <4>;
63 vmmc-supply = <&vcc_sd_reg>;
64 vqmmc-supply = <&vcc_sd_reg>;
65 };
66
67 regulators {
68 regulator@0 {
69 compatible = "regulator-fixed";
70 reg = <0>;
71 regulator-name = "usb_host_vbus";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 regulator-boot-on;
75 regulator-always-on;
76 gpio = <&gpio 178 0>;
77 };
78
79 vcc_sd_reg: regulator@1 {
80 compatible = "regulator-fixed";
81 reg = <1>;
82 regulator-name = "vcc_sd";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 regulator-boot-on;
86 regulator-always-on;
87 };
88 };
89};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 11b30db63ff2..54d6fce00a59 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -232,12 +244,10 @@
232 244
233 serial@70006000 { 245 serial@70006000 {
234 status = "okay"; 246 status = "okay";
235 clock-frequency = <216000000>;
236 }; 247 };
237 248
238 serial@70006200 { 249 serial@70006200 {
239 status = "okay"; 250 status = "okay";
240 clock-frequency = <216000000>;
241 }; 251 };
242 252
243 i2c@7000c000 { 253 i2c@7000c000 {
@@ -252,9 +262,9 @@
252 }; 262 };
253 }; 263 };
254 264
255 i2c@7000c400 { 265 hdmi_ddc: i2c@7000c400 {
256 status = "okay"; 266 status = "okay";
257 clock-frequency = <400000>; 267 clock-frequency = <100000>;
258 }; 268 };
259 269
260 nvec { 270 nvec {
@@ -369,13 +379,13 @@
369 regulator-max-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>;
370 }; 380 };
371 381
372 ldo7 { 382 hdmi_vdd_reg: ldo7 {
373 regulator-name = "+3.3vs_ldo7,avdd_hdmi"; 383 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
374 regulator-min-microvolt = <3300000>; 384 regulator-min-microvolt = <3300000>;
375 regulator-max-microvolt = <3300000>; 385 regulator-max-microvolt = <3300000>;
376 }; 386 };
377 387
378 ldo8 { 388 hdmi_pll_reg: ldo8 {
379 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; 389 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
380 regulator-min-microvolt = <1800000>; 390 regulator-min-microvolt = <1800000>;
381 regulator-max-microvolt = <1800000>; 391 regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 607bf0c6bf9c..37b3a57ec0f1 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -291,7 +303,6 @@
291 303
292 serial@70006300 { 304 serial@70006300 {
293 status = "okay"; 305 status = "okay";
294 clock-frequency = <216000000>;
295 }; 306 };
296 307
297 i2c@7000c000 { 308 i2c@7000c000 {
@@ -345,7 +356,7 @@
345 pinctrl-1 = <&state_i2cmux_pta>; 356 pinctrl-1 = <&state_i2cmux_pta>;
346 pinctrl-2 = <&state_i2cmux_idle>; 357 pinctrl-2 = <&state_i2cmux_idle>;
347 358
348 i2c@0 { 359 hdmi_ddc: i2c@0 {
349 reg = <0>; 360 reg = <0>;
350 #address-cells = <1>; 361 #address-cells = <1>;
351 #size-cells = <0>; 362 #size-cells = <0>;
@@ -463,13 +474,13 @@
463 regulator-max-microvolt = <1800000>; 474 regulator-max-microvolt = <1800000>;
464 }; 475 };
465 476
466 ldo7 { 477 hdmi_vdd_reg: ldo7 {
467 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 478 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
468 regulator-min-microvolt = <3300000>; 479 regulator-min-microvolt = <3300000>;
469 regulator-max-microvolt = <3300000>; 480 regulator-max-microvolt = <3300000>;
470 }; 481 };
471 482
472 ldo8 { 483 hdmi_pll_reg: ldo8 {
473 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 484 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
474 regulator-min-microvolt = <1800000>; 485 regulator-min-microvolt = <1800000>;
475 regulator-max-microvolt = <1800000>; 486 regulator-max-microvolt = <1800000>;
@@ -604,6 +615,145 @@
604 }; 615 };
605 }; 616 };
606 617
618 kbc {
619 status = "okay";
620 nvidia,debounce-delay-ms = <32>;
621 nvidia,repeat-delay-ms = <160>;
622 nvidia,ghost-filter;
623 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
624 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
625 linux,keymap = <0x00020011 /* KEY_W */
626 0x0003001F /* KEY_S */
627 0x0004001E /* KEY_A */
628 0x0005002C /* KEY_Z */
629 0x000701d0 /* KEY_FN */
630
631 0x0107007D /* KEY_LEFTMETA */
632 0x02060064 /* KEY_RIGHTALT */
633 0x02070038 /* KEY_LEFTALT */
634
635 0x03000006 /* KEY_5 */
636 0x03010005 /* KEY_4 */
637 0x03020013 /* KEY_R */
638 0x03030012 /* KEY_E */
639 0x03040021 /* KEY_F */
640 0x03050020 /* KEY_D */
641 0x0306002D /* KEY_X */
642
643 0x04000008 /* KEY_7 */
644 0x04010007 /* KEY_6 */
645 0x04020014 /* KEY_T */
646 0x04030023 /* KEY_H */
647 0x04040022 /* KEY_G */
648 0x0405002F /* KEY_V */
649 0x0406002E /* KEY_C */
650 0x04070039 /* KEY_SPACE */
651
652 0x0500000A /* KEY_9 */
653 0x05010009 /* KEY_8 */
654 0x05020016 /* KEY_U */
655 0x05030015 /* KEY_Y */
656 0x05040024 /* KEY_J */
657 0x05050031 /* KEY_N */
658 0x05060030 /* KEY_B */
659 0x0507002B /* KEY_BACKSLASH */
660
661 0x0600000C /* KEY_MINUS */
662 0x0601000B /* KEY_0 */
663 0x06020018 /* KEY_O */
664 0x06030017 /* KEY_I */
665 0x06040026 /* KEY_L */
666 0x06050025 /* KEY_K */
667 0x06060033 /* KEY_COMMA */
668 0x06070032 /* KEY_M */
669
670 0x0701000D /* KEY_EQUAL */
671 0x0702001B /* KEY_RIGHTBRACE */
672 0x0703001C /* KEY_ENTER */
673 0x0707008B /* KEY_MENU */
674
675 0x08040036 /* KEY_RIGHTSHIFT */
676 0x0805002A /* KEY_LEFTSHIFT */
677
678 0x09050061 /* KEY_RIGHTCTRL */
679 0x0907001D /* KEY_LEFTCTRL */
680
681 0x0B00001A /* KEY_LEFTBRACE */
682 0x0B010019 /* KEY_P */
683 0x0B020028 /* KEY_APOSTROPHE */
684 0x0B030027 /* KEY_SEMICOLON */
685 0x0B040035 /* KEY_SLASH */
686 0x0B050034 /* KEY_DOT */
687
688 0x0C000044 /* KEY_F10 */
689 0x0C010043 /* KEY_F9 */
690 0x0C02000E /* KEY_BACKSPACE */
691 0x0C030004 /* KEY_3 */
692 0x0C040003 /* KEY_2 */
693 0x0C050067 /* KEY_UP */
694 0x0C0600D2 /* KEY_PRINT */
695 0x0C070077 /* KEY_PAUSE */
696
697 0x0D00006E /* KEY_INSERT */
698 0x0D01006F /* KEY_DELETE */
699 0x0D030068 /* KEY_PAGEUP */
700 0x0D04006D /* KEY_PAGEDOWN */
701 0x0D05006A /* KEY_RIGHT */
702 0x0D06006C /* KEY_DOWN */
703 0x0D070069 /* KEY_LEFT */
704
705 0x0E000057 /* KEY_F11 */
706 0x0E010058 /* KEY_F12 */
707 0x0E020042 /* KEY_F8 */
708 0x0E030010 /* KEY_Q */
709 0x0E04003E /* KEY_F4 */
710 0x0E05003D /* KEY_F3 */
711 0x0E060002 /* KEY_1 */
712 0x0E070041 /* KEY_F7 */
713
714 0x0F000001 /* KEY_ESC */
715 0x0F010029 /* KEY_GRAVE */
716 0x0F02003F /* KEY_F5 */
717 0x0F03000F /* KEY_TAB */
718 0x0F04003B /* KEY_F1 */
719 0x0F05003C /* KEY_F2 */
720 0x0F06003A /* KEY_CAPSLOCK */
721 0x0F070040 /* KEY_F6 */
722
723 /* Software Handled Function Keys */
724 0x14000047 /* KEY_KP7 */
725
726 0x15000049 /* KEY_KP9 */
727 0x15010048 /* KEY_KP8 */
728 0x1502004B /* KEY_KP4 */
729 0x1504004F /* KEY_KP1 */
730
731 0x1601004E /* KEY_KPSLASH */
732 0x1602004D /* KEY_KP6 */
733 0x1603004C /* KEY_KP5 */
734 0x16040051 /* KEY_KP3 */
735 0x16050050 /* KEY_KP2 */
736 0x16070052 /* KEY_KP0 */
737
738 0x1B010037 /* KEY_KPASTERISK */
739 0x1B03004A /* KEY_KPMINUS */
740 0x1B04004E /* KEY_KPPLUS */
741 0x1B050053 /* KEY_KPDOT */
742
743 0x1C050073 /* KEY_VOLUMEUP */
744
745 0x1D030066 /* KEY_HOME */
746 0x1D04006B /* KEY_END */
747 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
748 0x1D060072 /* KEY_VOLUMEDOWN */
749 0x1D0700E1 /* KEY_BRIGHTNESSUP */
750
751 0x1E000045 /* KEY_NUMLOCK */
752 0x1E010046 /* KEY_SCROLLLOCK */
753 0x1E020071 /* KEY_MUTE */
754
755 0x1F04008A>; /* KEY_HELP */
756 };
607 regulators { 757 regulators {
608 compatible = "simple-bus"; 758 compatible = "simple-bus";
609 #address-cells = <1>; 759 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index a239ccdfaa52..4766abae7a72 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -276,7 +276,6 @@
276 }; 276 };
277 277
278 serial@70006300 { 278 serial@70006300 {
279 clock-frequency = <216000000>;
280 status = "okay"; 279 status = "okay";
281 }; 280 };
282 281
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index e47cf6a58b6f..5d79e4fc49a6 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -249,6 +249,11 @@
249 "ld23_22"; 249 "ld23_22";
250 nvidia,pull = <1>; 250 nvidia,pull = <1>;
251 }; 251 };
252 conf_spif {
253 nvidia,pins = "spif";
254 nvidia,pull = <1>;
255 nvidia,tristate = <0>;
256 };
252 }; 257 };
253 }; 258 };
254 259
@@ -258,7 +263,6 @@
258 263
259 serial@70006000 { 264 serial@70006000 {
260 status = "okay"; 265 status = "okay";
261 clock-frequency = <216000000>;
262 }; 266 };
263 267
264 dvi_ddc: i2c@7000c000 { 268 dvi_ddc: i2c@7000c000 {
@@ -326,6 +330,11 @@
326 bus-width = <4>; 330 bus-width = <4>;
327 }; 331 };
328 332
333 poweroff {
334 compatible = "gpio-poweroff";
335 gpios = <&gpio 191 1>; /* gpio PX7, active low */
336 };
337
329 regulators { 338 regulators {
330 compatible = "simple-bus"; 339 compatible = "simple-bus";
331 #address-cells = <1>; 340 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index f6c61d10fd27..425c89000c20 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -3,13 +3,25 @@
3/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board"; 6 model = "NVIDIA Tegra20 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20"; 7 compatible = "nvidia,ventana", "nvidia,tegra20";
8 8
9 memory { 9 memory {
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -288,7 +300,6 @@
288 300
289 serial@70006300 { 301 serial@70006300 {
290 status = "okay"; 302 status = "okay";
291 clock-frequency = <216000000>;
292 }; 303 };
293 304
294 i2c@7000c000 { 305 i2c@7000c000 {
@@ -320,7 +331,7 @@
320 331
321 i2c@7000c400 { 332 i2c@7000c400 {
322 status = "okay"; 333 status = "okay";
323 clock-frequency = <400000>; 334 clock-frequency = <100000>;
324 }; 335 };
325 336
326 i2cmux { 337 i2cmux {
@@ -335,7 +346,7 @@
335 pinctrl-1 = <&state_i2cmux_pta>; 346 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>; 347 pinctrl-2 = <&state_i2cmux_idle>;
337 348
338 i2c@0 { 349 hdmi_ddc: i2c@0 {
339 reg = <0>; 350 reg = <0>;
340 #address-cells = <1>; 351 #address-cells = <1>;
341 #size-cells = <0>; 352 #size-cells = <0>;
@@ -446,13 +457,13 @@
446 regulator-max-microvolt = <1800000>; 457 regulator-max-microvolt = <1800000>;
447 }; 458 };
448 459
449 ldo7 { 460 hdmi_vdd_reg: ldo7 {
450 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 461 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
451 regulator-min-microvolt = <3300000>; 462 regulator-min-microvolt = <3300000>;
452 regulator-max-microvolt = <3300000>; 463 regulator-max-microvolt = <3300000>;
453 }; 464 };
454 465
455 ldo8 { 466 hdmi_pll_reg: ldo8 {
456 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 467 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
457 regulator-min-microvolt = <1800000>; 468 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>; 469 regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 20d576ecd555..ea57c0f6dcce 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -3,7 +3,7 @@
3/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra2 Whistler evaluation board"; 6 model = "NVIDIA Tegra20 Whistler evaluation board";
7 compatible = "nvidia,whistler", "nvidia,tegra20"; 7 compatible = "nvidia,whistler", "nvidia,tegra20";
8 8
9 memory { 9 memory {
@@ -255,7 +255,6 @@
255 255
256 serial@70006000 { 256 serial@70006000 {
257 status = "okay"; 257 status = "okay";
258 clock-frequency = <216000000>;
259 }; 258 };
260 259
261 hdmi_ddc: i2c@7000c400 { 260 hdmi_ddc: i2c@7000c400 {
@@ -520,6 +519,18 @@
520 bus-width = <8>; 519 bus-width = <8>;
521 }; 520 };
522 521
522 kbc {
523 status = "okay";
524 nvidia,debounce-delay-ms = <20>;
525 nvidia,repeat-delay-ms = <160>;
526 nvidia,kbc-row-pins = <0 1 2>;
527 nvidia,kbc-col-pins = <16 17>;
528 linux,keymap = <0x00000074 /* KEY_POWER */
529 0x01000066 /* KEY_HOME */
530 0x0101009E /* KEY_BACK */
531 0x0201008B>; /* KEY_MENU */
532 };
533
523 regulators { 534 regulators {
524 compatible = "simple-bus"; 535 compatible = "simple-bus";
525 #address-cells = <1>; 536 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 2e7c83c7253b..cdb8da0b6983 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,14 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
7 host1x { 15 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus"; 16 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>; 17 reg = <0x50000000 0x00024000>;
@@ -112,15 +120,6 @@
112 interrupts = <1 13 0x304>; 120 interrupts = <1 13 0x304>;
113 }; 121 };
114 122
115 cache-controller@50043000 {
116 compatible = "arm,pl310-cache";
117 reg = <0x50043000 0x1000>;
118 arm,data-latency = <5 5 2>;
119 arm,tag-latency = <4 4 2>;
120 cache-unified;
121 cache-level = <2>;
122 };
123
124 intc: interrupt-controller { 123 intc: interrupt-controller {
125 compatible = "arm,cortex-a9-gic"; 124 compatible = "arm,cortex-a9-gic";
126 reg = <0x50041000 0x1000 125 reg = <0x50041000 0x1000
@@ -129,6 +128,15 @@
129 #interrupt-cells = <3>; 128 #interrupt-cells = <3>;
130 }; 129 };
131 130
131 cache-controller {
132 compatible = "arm,pl310-cache";
133 reg = <0x50043000 0x1000>;
134 arm,data-latency = <5 5 2>;
135 arm,tag-latency = <4 4 2>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
132 timer@60005000 { 140 timer@60005000 {
133 compatible = "nvidia,tegra20-timer"; 141 compatible = "nvidia,tegra20-timer";
134 reg = <0x60005000 0x60>; 142 reg = <0x60005000 0x60>;
@@ -199,6 +207,15 @@
199 compatible = "nvidia,tegra20-das"; 207 compatible = "nvidia,tegra20-das";
200 reg = <0x70000c00 0x80>; 208 reg = <0x70000c00 0x80>;
201 }; 209 };
210
211 tegra_ac97: ac97 {
212 compatible = "nvidia,tegra20-ac97";
213 reg = <0x70002000 0x200>;
214 interrupts = <0 81 0x04>;
215 nvidia,dma-request-selector = <&apbdma 12>;
216 clocks = <&tegra_car 3>;
217 status = "disabled";
218 };
202 219
203 tegra_i2s1: i2s@70002800 { 220 tegra_i2s1: i2s@70002800 {
204 compatible = "nvidia,tegra20-i2s"; 221 compatible = "nvidia,tegra20-i2s";
@@ -218,47 +235,64 @@
218 status = "disabled"; 235 status = "disabled";
219 }; 236 };
220 237
221 serial@70006000 { 238 /*
239 * There are two serial driver i.e. 8250 based simple serial
240 * driver and APB DMA based serial driver for higher baudrate
241 * and performace. To enable the 8250 based driver, the compatible
242 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
243 * driver, the comptible is "nvidia,tegra20-hsuart".
244 */
245 uarta: serial@70006000 {
222 compatible = "nvidia,tegra20-uart"; 246 compatible = "nvidia,tegra20-uart";
223 reg = <0x70006000 0x40>; 247 reg = <0x70006000 0x40>;
224 reg-shift = <2>; 248 reg-shift = <2>;
225 interrupts = <0 36 0x04>; 249 interrupts = <0 36 0x04>;
250 clock-frequency = <216000000>;
251 nvidia,dma-request-selector = <&apbdma 8>;
226 clocks = <&tegra_car 6>; 252 clocks = <&tegra_car 6>;
227 status = "disabled"; 253 status = "disabled";
228 }; 254 };
229 255
230 serial@70006040 { 256 uartb: serial@70006040 {
231 compatible = "nvidia,tegra20-uart"; 257 compatible = "nvidia,tegra20-uart";
232 reg = <0x70006040 0x40>; 258 reg = <0x70006040 0x40>;
233 reg-shift = <2>; 259 reg-shift = <2>;
234 interrupts = <0 37 0x04>; 260 interrupts = <0 37 0x04>;
261 clock-frequency = <216000000>;
262 nvidia,dma-request-selector = <&apbdma 9>;
235 clocks = <&tegra_car 96>; 263 clocks = <&tegra_car 96>;
236 status = "disabled"; 264 status = "disabled";
237 }; 265 };
238 266
239 serial@70006200 { 267 uartc: serial@70006200 {
240 compatible = "nvidia,tegra20-uart"; 268 compatible = "nvidia,tegra20-uart";
241 reg = <0x70006200 0x100>; 269 reg = <0x70006200 0x100>;
242 reg-shift = <2>; 270 reg-shift = <2>;
243 interrupts = <0 46 0x04>; 271 interrupts = <0 46 0x04>;
272 clock-frequency = <216000000>;
273 nvidia,dma-request-selector = <&apbdma 10>;
244 clocks = <&tegra_car 55>; 274 clocks = <&tegra_car 55>;
245 status = "disabled"; 275 status = "disabled";
246 }; 276 };
247 277
248 serial@70006300 { 278 uartd: serial@70006300 {
249 compatible = "nvidia,tegra20-uart"; 279 compatible = "nvidia,tegra20-uart";
250 reg = <0x70006300 0x100>; 280 reg = <0x70006300 0x100>;
251 reg-shift = <2>; 281 reg-shift = <2>;
252 interrupts = <0 90 0x04>; 282 interrupts = <0 90 0x04>;
283 clock-frequency = <216000000>;
284 nvidia,dma-request-selector = <&apbdma 19>;
253 clocks = <&tegra_car 65>; 285 clocks = <&tegra_car 65>;
254 status = "disabled"; 286 status = "disabled";
255 }; 287 };
256 288
257 serial@70006400 { 289 uarte: serial@70006400 {
258 compatible = "nvidia,tegra20-uart"; 290 compatible = "nvidia,tegra20-uart";
259 reg = <0x70006400 0x100>; 291 reg = <0x70006400 0x100>;
260 reg-shift = <2>; 292 reg-shift = <2>;
261 interrupts = <0 91 0x04>; 293 interrupts = <0 91 0x04>;
294 clock-frequency = <216000000>;
295 nvidia,dma-request-selector = <&apbdma 20>;
262 clocks = <&tegra_car 66>; 296 clocks = <&tegra_car 66>;
263 status = "disabled"; 297 status = "disabled";
264 }; 298 };
@@ -375,6 +409,14 @@
375 status = "disabled"; 409 status = "disabled";
376 }; 410 };
377 411
412 kbc {
413 compatible = "nvidia,tegra20-kbc";
414 reg = <0x7000e200 0x100>;
415 interrupts = <0 85 0x04>;
416 clocks = <&tegra_car 36>;
417 status = "disabled";
418 };
419
378 pmc { 420 pmc {
379 compatible = "nvidia,tegra20-pmc"; 421 compatible = "nvidia,tegra20-pmc";
380 reg = <0x7000e400 0x400>; 422 reg = <0x7000e400 0x400>;
@@ -387,7 +429,7 @@
387 interrupts = <0 77 0x04>; 429 interrupts = <0 77 0x04>;
388 }; 430 };
389 431
390 gart { 432 iommu {
391 compatible = "nvidia,tegra20-gart"; 433 compatible = "nvidia,tegra20-gart";
392 reg = <0x7000f024 0x00000018 /* controller registers */ 434 reg = <0x7000f024 0x00000018 /* controller registers */
393 0x58000000 0x02000000>; /* GART aperture */ 435 0x58000000 0x02000000>; /* GART aperture */
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
new file mode 100644
index 000000000000..8ff2ff20e4a3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -0,0 +1,373 @@
1/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Beaver evaluation board";
7 compatible = "nvidia,beaver", "nvidia,tegra30";
8
9 memory {
10 reg = <0x80000000 0x80000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc3_clk_pa6 {
35 nvidia,pins = "sdmmc3_clk_pa6";
36 nvidia,function = "sdmmc3";
37 nvidia,pull = <0>;
38 nvidia,tristate = <0>;
39 };
40 sdmmc3_cmd_pa7 {
41 nvidia,pins = "sdmmc3_cmd_pa7",
42 "sdmmc3_dat0_pb7",
43 "sdmmc3_dat1_pb6",
44 "sdmmc3_dat2_pb5",
45 "sdmmc3_dat3_pb4";
46 nvidia,function = "sdmmc3";
47 nvidia,pull = <2>;
48 nvidia,tristate = <0>;
49 };
50 sdmmc4_clk_pcc4 {
51 nvidia,pins = "sdmmc4_clk_pcc4",
52 "sdmmc4_rst_n_pcc3";
53 nvidia,function = "sdmmc4";
54 nvidia,pull = <0>;
55 nvidia,tristate = <0>;
56 };
57 sdmmc4_dat0_paa0 {
58 nvidia,pins = "sdmmc4_dat0_paa0",
59 "sdmmc4_dat1_paa1",
60 "sdmmc4_dat2_paa2",
61 "sdmmc4_dat3_paa3",
62 "sdmmc4_dat4_paa4",
63 "sdmmc4_dat5_paa5",
64 "sdmmc4_dat6_paa6",
65 "sdmmc4_dat7_paa7";
66 nvidia,function = "sdmmc4";
67 nvidia,pull = <2>;
68 nvidia,tristate = <0>;
69 };
70 dap2_fs_pa2 {
71 nvidia,pins = "dap2_fs_pa2",
72 "dap2_sclk_pa3",
73 "dap2_din_pa4",
74 "dap2_dout_pa5";
75 nvidia,function = "i2s1";
76 nvidia,pull = <0>;
77 nvidia,tristate = <0>;
78 };
79 sdio3 {
80 nvidia,pins = "drive_sdio3";
81 nvidia,high-speed-mode = <0>;
82 nvidia,schmitt = <0>;
83 nvidia,pull-down-strength = <46>;
84 nvidia,pull-up-strength = <42>;
85 nvidia,slew-rate-rising = <1>;
86 nvidia,slew-rate-falling = <1>;
87 };
88 };
89 };
90
91 serial@70006000 {
92 status = "okay";
93 };
94
95 i2c@7000c000 {
96 status = "okay";
97 clock-frequency = <100000>;
98 };
99
100 i2c@7000c400 {
101 status = "okay";
102 clock-frequency = <100000>;
103 };
104
105 i2c@7000c500 {
106 status = "okay";
107 clock-frequency = <100000>;
108 };
109
110 i2c@7000c700 {
111 status = "okay";
112 clock-frequency = <100000>;
113 };
114
115 i2c@7000d000 {
116 status = "okay";
117 clock-frequency = <100000>;
118
119 tps62361 {
120 compatible = "ti,tps62361";
121 reg = <0x60>;
122
123 regulator-name = "tps62361-vout";
124 regulator-min-microvolt = <500000>;
125 regulator-max-microvolt = <1500000>;
126 regulator-boot-on;
127 regulator-always-on;
128 ti,vsel0-state-high;
129 ti,vsel1-state-high;
130 };
131
132 pmic: tps65911@2d {
133 compatible = "ti,tps65911";
134 reg = <0x2d>;
135
136 interrupts = <0 86 0x4>;
137 #interrupt-cells = <2>;
138 interrupt-controller;
139
140 ti,system-power-controller;
141
142 #gpio-cells = <2>;
143 gpio-controller;
144
145 vcc1-supply = <&vdd_5v_in_reg>;
146 vcc2-supply = <&vdd_5v_in_reg>;
147 vcc3-supply = <&vio_reg>;
148 vcc4-supply = <&vdd_5v_in_reg>;
149 vcc5-supply = <&vdd_5v_in_reg>;
150 vcc6-supply = <&vdd2_reg>;
151 vcc7-supply = <&vdd_5v_in_reg>;
152 vccio-supply = <&vdd_5v_in_reg>;
153
154 regulators {
155 #address-cells = <1>;
156 #size-cells = <0>;
157
158 vdd1_reg: vdd1 {
159 regulator-name = "vddio_ddr_1v2";
160 regulator-min-microvolt = <1200000>;
161 regulator-max-microvolt = <1200000>;
162 regulator-always-on;
163 };
164
165 vdd2_reg: vdd2 {
166 regulator-name = "vdd_1v5_gen";
167 regulator-min-microvolt = <1500000>;
168 regulator-max-microvolt = <1500000>;
169 regulator-always-on;
170 };
171
172 vddctrl_reg: vddctrl {
173 regulator-name = "vdd_cpu,vdd_sys";
174 regulator-min-microvolt = <1000000>;
175 regulator-max-microvolt = <1000000>;
176 regulator-always-on;
177 };
178
179 vio_reg: vio {
180 regulator-name = "vdd_1v8_gen";
181 regulator-min-microvolt = <1800000>;
182 regulator-max-microvolt = <1800000>;
183 regulator-always-on;
184 };
185
186 ldo1_reg: ldo1 {
187 regulator-name = "vdd_pexa,vdd_pexb";
188 regulator-min-microvolt = <1050000>;
189 regulator-max-microvolt = <1050000>;
190 };
191
192 ldo2_reg: ldo2 {
193 regulator-name = "vdd_sata,avdd_plle";
194 regulator-min-microvolt = <1050000>;
195 regulator-max-microvolt = <1050000>;
196 };
197
198 /* LDO3 is not connected to anything */
199
200 ldo4_reg: ldo4 {
201 regulator-name = "vdd_rtc";
202 regulator-min-microvolt = <1200000>;
203 regulator-max-microvolt = <1200000>;
204 regulator-always-on;
205 };
206
207 ldo5_reg: ldo5 {
208 regulator-name = "vddio_sdmmc,avdd_vdac";
209 regulator-min-microvolt = <3300000>;
210 regulator-max-microvolt = <3300000>;
211 regulator-always-on;
212 };
213
214 ldo6_reg: ldo6 {
215 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
216 regulator-min-microvolt = <1200000>;
217 regulator-max-microvolt = <1200000>;
218 };
219
220 ldo7_reg: ldo7 {
221 regulator-name = "vdd_pllm,x,u,a_p_c_s";
222 regulator-min-microvolt = <1200000>;
223 regulator-max-microvolt = <1200000>;
224 regulator-always-on;
225 };
226
227 ldo8_reg: ldo8 {
228 regulator-name = "vdd_ddr_hs";
229 regulator-min-microvolt = <1000000>;
230 regulator-max-microvolt = <1000000>;
231 regulator-always-on;
232 };
233 };
234 };
235 };
236
237 spi@7000da00 {
238 status = "okay";
239 spi-max-frequency = <25000000>;
240 spi-flash@1 {
241 compatible = "winbond,w25q32";
242 reg = <1>;
243 spi-max-frequency = <20000000>;
244 };
245 };
246
247 ahub {
248 i2s@70080400 {
249 status = "okay";
250 };
251 };
252
253 pmc {
254 status = "okay";
255 nvidia,invert-interrupt;
256 };
257
258 sdhci@78000000 {
259 status = "okay";
260 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
261 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
262 power-gpios = <&gpio 31 0>; /* gpio PD7 */
263 bus-width = <4>;
264 };
265
266 sdhci@78000600 {
267 status = "okay";
268 bus-width = <8>;
269 };
270
271 regulators {
272 compatible = "simple-bus";
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 vdd_5v_in_reg: regulator@0 {
277 compatible = "regulator-fixed";
278 reg = <0>;
279 regulator-name = "vdd_5v_in";
280 regulator-min-microvolt = <5000000>;
281 regulator-max-microvolt = <5000000>;
282 regulator-always-on;
283 };
284
285 chargepump_5v_reg: regulator@1 {
286 compatible = "regulator-fixed";
287 reg = <1>;
288 regulator-name = "chargepump_5v";
289 regulator-min-microvolt = <5000000>;
290 regulator-max-microvolt = <5000000>;
291 regulator-boot-on;
292 regulator-always-on;
293 enable-active-high;
294 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
295 };
296
297 ddr_reg: regulator@2 {
298 compatible = "regulator-fixed";
299 reg = <2>;
300 regulator-name = "vdd_ddr";
301 regulator-min-microvolt = <1500000>;
302 regulator-max-microvolt = <1500000>;
303 regulator-always-on;
304 regulator-boot-on;
305 enable-active-high;
306 gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
307 vin-supply = <&vdd_5v_in_reg>;
308 };
309
310 vdd_5v_sata_reg: regulator@3 {
311 compatible = "regulator-fixed";
312 reg = <3>;
313 regulator-name = "vdd_5v_sata";
314 regulator-min-microvolt = <5000000>;
315 regulator-max-microvolt = <5000000>;
316 regulator-always-on;
317 regulator-boot-on;
318 enable-active-high;
319 gpio = <&gpio 30 0>; /* gpio PD6 */
320 vin-supply = <&vdd_5v_in_reg>;
321 };
322
323 usb1_vbus_reg: regulator@4 {
324 compatible = "regulator-fixed";
325 reg = <4>;
326 regulator-name = "usb1_vbus";
327 regulator-min-microvolt = <5000000>;
328 regulator-max-microvolt = <5000000>;
329 enable-active-high;
330 gpio = <&gpio 68 0>; /* GPIO PI4 */
331 gpio-open-drain;
332 vin-supply = <&vdd_5v_in_reg>;
333 };
334
335 usb3_vbus_reg: regulator@5 {
336 compatible = "regulator-fixed";
337 reg = <5>;
338 regulator-name = "usb3_vbus";
339 regulator-min-microvolt = <5000000>;
340 regulator-max-microvolt = <5000000>;
341 enable-active-high;
342 gpio = <&gpio 63 0>; /* GPIO PH7 */
343 gpio-open-drain;
344 vin-supply = <&vdd_5v_in_reg>;
345 };
346
347 sys_3v3_reg: regulator@6 {
348 compatible = "regulator-fixed";
349 reg = <6>;
350 regulator-name = "sys_3v3,vdd_3v3_alw";
351 regulator-min-microvolt = <3300000>;
352 regulator-max-microvolt = <3300000>;
353 regulator-always-on;
354 regulator-boot-on;
355 enable-active-high;
356 gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
357 vin-supply = <&vdd_5v_in_reg>;
358 };
359
360 sys_3v3_pexs_reg: regulator@7 {
361 compatible = "regulator-fixed";
362 reg = <7>;
363 regulator-name = "sys_3v3_pexs";
364 regulator-min-microvolt = <3300000>;
365 regulator-max-microvolt = <3300000>;
366 regulator-always-on;
367 regulator-boot-on;
368 enable-active-high;
369 gpio = <&gpio 95 0>; /* gpio PL7 */
370 vin-supply = <&sys_3v3_reg>;
371 };
372 };
373};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index bdb2a660f376..17499272a4ef 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -106,12 +106,25 @@
106 nvidia,slew-rate-rising = <1>; 106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>; 107 nvidia,slew-rate-falling = <1>;
108 }; 108 };
109 uart3_txd_pw6 {
110 nvidia,pins = "uart3_txd_pw6",
111 "uart3_cts_n_pa1",
112 "uart3_rts_n_pc0",
113 "uart3_rxd_pw7";
114 nvidia,function = "uartc";
115 nvidia,pull = <0>;
116 nvidia,tristate = <0>;
117 };
109 }; 118 };
110 }; 119 };
111 120
112 serial@70006000 { 121 serial@70006000 {
113 status = "okay"; 122 status = "okay";
114 clock-frequency = <408000000>; 123 };
124
125 serial@70006200 {
126 compatible = "nvidia,tegra30-hsuart";
127 status = "okay";
115 }; 128 };
116 129
117 i2c@7000c000 { 130 i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2de8b919d78c..572a45bab93b 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,14 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
7 host1x { 15 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus"; 16 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>; 17 reg = <0x50000000 0x00024000>;
@@ -113,15 +121,6 @@
113 interrupts = <1 13 0xf04>; 121 interrupts = <1 13 0xf04>;
114 }; 122 };
115 123
116 cache-controller@50043000 {
117 compatible = "arm,pl310-cache";
118 reg = <0x50043000 0x1000>;
119 arm,data-latency = <6 6 2>;
120 arm,tag-latency = <5 5 2>;
121 cache-unified;
122 cache-level = <2>;
123 };
124
125 intc: interrupt-controller { 124 intc: interrupt-controller {
126 compatible = "arm,cortex-a9-gic"; 125 compatible = "arm,cortex-a9-gic";
127 reg = <0x50041000 0x1000 126 reg = <0x50041000 0x1000
@@ -130,6 +129,15 @@
130 #interrupt-cells = <3>; 129 #interrupt-cells = <3>;
131 }; 130 };
132 131
132 cache-controller {
133 compatible = "arm,pl310-cache";
134 reg = <0x50043000 0x1000>;
135 arm,data-latency = <6 6 2>;
136 arm,tag-latency = <5 5 2>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
133 timer@60005000 { 141 timer@60005000 {
134 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 142 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
135 reg = <0x60005000 0x400>; 143 reg = <0x60005000 0x400>;
@@ -191,7 +199,7 @@
191 }; 199 };
192 200
193 gpio: gpio { 201 gpio: gpio {
194 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; 202 compatible = "nvidia,tegra30-gpio";
195 reg = <0x6000d000 0x1000>; 203 reg = <0x6000d000 0x1000>;
196 interrupts = <0 32 0x04 204 interrupts = <0 32 0x04
197 0 33 0x04 205 0 33 0x04
@@ -213,47 +221,65 @@
213 0x70003000 0x3e4>; /* Mux registers */ 221 0x70003000 0x3e4>; /* Mux registers */
214 }; 222 };
215 223
216 serial@70006000 { 224 /*
225 * There are two serial driver i.e. 8250 based simple serial
226 * driver and APB DMA based serial driver for higher baudrate
227 * and performace. To enable the 8250 based driver, the compatible
228 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
229 * the APB DMA based serial driver, the comptible is
230 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
231 */
232 uarta: serial@70006000 {
217 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 233 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
218 reg = <0x70006000 0x40>; 234 reg = <0x70006000 0x40>;
219 reg-shift = <2>; 235 reg-shift = <2>;
220 interrupts = <0 36 0x04>; 236 interrupts = <0 36 0x04>;
237 clock-frequency = <408000000>;
238 nvidia,dma-request-selector = <&apbdma 8>;
221 clocks = <&tegra_car 6>; 239 clocks = <&tegra_car 6>;
222 status = "disabled"; 240 status = "disabled";
223 }; 241 };
224 242
225 serial@70006040 { 243 uartb: serial@70006040 {
226 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 244 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
227 reg = <0x70006040 0x40>; 245 reg = <0x70006040 0x40>;
228 reg-shift = <2>; 246 reg-shift = <2>;
247 clock-frequency = <408000000>;
229 interrupts = <0 37 0x04>; 248 interrupts = <0 37 0x04>;
249 nvidia,dma-request-selector = <&apbdma 9>;
230 clocks = <&tegra_car 160>; 250 clocks = <&tegra_car 160>;
231 status = "disabled"; 251 status = "disabled";
232 }; 252 };
233 253
234 serial@70006200 { 254 uartc: serial@70006200 {
235 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 255 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
236 reg = <0x70006200 0x100>; 256 reg = <0x70006200 0x100>;
237 reg-shift = <2>; 257 reg-shift = <2>;
258 clock-frequency = <408000000>;
238 interrupts = <0 46 0x04>; 259 interrupts = <0 46 0x04>;
260 nvidia,dma-request-selector = <&apbdma 10>;
239 clocks = <&tegra_car 55>; 261 clocks = <&tegra_car 55>;
240 status = "disabled"; 262 status = "disabled";
241 }; 263 };
242 264
243 serial@70006300 { 265 uartd: serial@70006300 {
244 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 266 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
245 reg = <0x70006300 0x100>; 267 reg = <0x70006300 0x100>;
246 reg-shift = <2>; 268 reg-shift = <2>;
269 clock-frequency = <408000000>;
247 interrupts = <0 90 0x04>; 270 interrupts = <0 90 0x04>;
271 nvidia,dma-request-selector = <&apbdma 19>;
248 clocks = <&tegra_car 65>; 272 clocks = <&tegra_car 65>;
249 status = "disabled"; 273 status = "disabled";
250 }; 274 };
251 275
252 serial@70006400 { 276 uarte: serial@70006400 {
253 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 277 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
254 reg = <0x70006400 0x100>; 278 reg = <0x70006400 0x100>;
255 reg-shift = <2>; 279 reg-shift = <2>;
280 clock-frequency = <408000000>;
256 interrupts = <0 91 0x04>; 281 interrupts = <0 91 0x04>;
282 nvidia,dma-request-selector = <&apbdma 20>;
257 clocks = <&tegra_car 66>; 283 clocks = <&tegra_car 66>;
258 status = "disabled"; 284 status = "disabled";
259 }; 285 };
@@ -392,6 +418,14 @@
392 status = "disabled"; 418 status = "disabled";
393 }; 419 };
394 420
421 kbc {
422 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
423 reg = <0x7000e200 0x100>;
424 interrupts = <0 85 0x04>;
425 clocks = <&tegra_car 36>;
426 status = "disabled";
427 };
428
395 pmc { 429 pmc {
396 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; 430 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
397 reg = <0x7000e400 0x400>; 431 reg = <0x7000e400 0x400>;
@@ -406,7 +440,7 @@
406 interrupts = <0 77 0x04>; 440 interrupts = <0 77 0x04>;
407 }; 441 };
408 442
409 smmu { 443 iommu {
410 compatible = "nvidia,tegra30-smmu"; 444 compatible = "nvidia,tegra30-smmu";
411 reg = <0x7000f010 0x02c 445 reg = <0x7000f010 0x02c
412 0x7000f1f0 0x010 446 0x7000f1f0 0x010
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 09:22:43 -0400