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authorOlof Johansson <olof@lixom.net>2013-06-14 21:09:41 -0400
committerOlof Johansson <olof@lixom.net>2013-06-14 21:09:41 -0400
commit36d29fb57ccbf3cea2e46fea2ef5f0ffc22308e4 (patch)
tree60038ef374cbfd97b1f75c14c6b44f5dde9c2d8d /arch/arm/boot
parent3b2e6296abeefb6f602e1cf1bd67e4e3a9b9ee7e (diff)
parent23037bbd9661b53236ebe934c77952e8f73f1c7a (diff)
Merge tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From Stephen Warren: ARM: tegra: device tree updates This branch contains all device tree updates for Tegra boards. The changes are: * Converted all DT files to use the C pre-processor, to support the use of named constants. This included use of defines for GPIO, IRQ, and clock constants. * Enabling new features such as: - SPI on Dalmore. - Audio on Dalmore and Beaver. - gpio-leds on Beaver. - Power-supply/batter linkage on Dalmore. * A minor fix to the RAM size node on Beaver. It is based on previous pull request tegra-for-3.11-deps-for-usb followed by a merge of tegra-for-3.11-deps-for-clk. * tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (21 commits) ARM: tegra: enable audio on Beaver ARM: tegra: enable audio on Dalmore ARM: tegra: add power-supplies link between battery and charger ARM: tegra: add audio-related nodes to Tegra114 DT ARM: tegra114: convert device tree files to use CLK defines ARM: tegra30: convert device tree files to use CLK defines ARM: tegra20: convert device tree files to use CLK defines ARM: tegra: Add charger subnode to tps65090 node ARM: tegra: convert device tree files to use IRQ defines ARM: tegra: convert device tree files to use GPIO defines ARM: tegra: create a DT header defining GPIO IDs ARM: tegra: use #include for all device trees ARM: tegra: Add gpio-leds to Tegra30 Beaver ARM: tegra: fix memory size on Beaver ARM: tegra: enable spi4 on Dalmore ARM: tegra114: create a DT header defining CLK IDs ARM: tegra30: create a DT header defining CLK IDs ARM: tegra20: create a DT header defining CLK IDs ARM: tegra: update device trees for USB binding rework ARM: tegra: modify ULPI reset GPIO properties ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts71
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts2
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi277
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi29
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts67
-rw-r--r--arch/arm/boot/dts/tegra20-iris-512.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts12
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts48
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts12
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts69
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts13
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts46
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts60
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts47
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi285
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts68
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts16
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts18
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi47
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi288
21 files changed, 950 insertions, 553 deletions
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 72c1f27af7f3..cb640eb6c932 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra114.dtsi" 3#include "tegra114.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra114 Dalmore evaluation board"; 6 model = "NVIDIA Tegra114 Dalmore evaluation board";
@@ -727,6 +727,16 @@
727 battery-name = "battery"; 727 battery-name = "battery";
728 sbs,i2c-retry-count = <2>; 728 sbs,i2c-retry-count = <2>;
729 sbs,poll-retry-count = <100>; 729 sbs,poll-retry-count = <100>;
730 power-supplies = <&charger>;
731 };
732
733 rt5640: rt5640 {
734 compatible = "realtek,rt5640";
735 reg = <0x1c>;
736 interrupt-parent = <&gpio>;
737 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
738 realtek,ldo1-en-gpios =
739 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
730 }; 740 };
731 }; 741 };
732 742
@@ -748,7 +758,7 @@
748 compatible = "ti,tps65090"; 758 compatible = "ti,tps65090";
749 reg = <0x48>; 759 reg = <0x48>;
750 interrupt-parent = <&gpio>; 760 interrupt-parent = <&gpio>;
751 interrupts = <72 0x04>; /* gpio PJ0 */ 761 interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
752 762
753 vsys1-supply = <&vdd_ac_bat_reg>; 763 vsys1-supply = <&vdd_ac_bat_reg>;
754 vsys2-supply = <&vdd_ac_bat_reg>; 764 vsys2-supply = <&vdd_ac_bat_reg>;
@@ -763,6 +773,11 @@
763 vsys-l1-supply = <&vdd_ac_bat_reg>; 773 vsys-l1-supply = <&vdd_ac_bat_reg>;
764 vsys-l2-supply = <&vdd_ac_bat_reg>; 774 vsys-l2-supply = <&vdd_ac_bat_reg>;
765 775
776 charger: charger {
777 compatible = "ti,tps65090-charger";
778 ti,enable-low-current-chrg;
779 };
780
766 regulators { 781 regulators {
767 tps65090_dcdc1_reg: dcdc1 { 782 tps65090_dcdc1_reg: dcdc1 {
768 regulator-name = "vdd-sys-5v0"; 783 regulator-name = "vdd-sys-5v0";
@@ -823,12 +838,28 @@
823 }; 838 };
824 }; 839 };
825 840
841 spi@7000da00 {
842 status = "okay";
843 spi-max-frequency = <25000000>;
844 spi-flash@0 {
845 compatible = "winbond,w25q32dw";
846 reg = <0>;
847 spi-max-frequency = <20000000>;
848 };
849 };
850
826 pmc { 851 pmc {
827 nvidia,invert-interrupt; 852 nvidia,invert-interrupt;
828 }; 853 };
829 854
855 ahub {
856 i2s@70080400 {
857 status = "okay";
858 };
859 };
860
830 sdhci@78000400 { 861 sdhci@78000400 {
831 cd-gpios = <&gpio 170 1>; /* gpio PV2 */ 862 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
832 bus-width = <4>; 863 bus-width = <4>;
833 status = "okay"; 864 status = "okay";
834 }; 865 };
@@ -873,7 +904,7 @@
873 regulator-min-microvolt = <1800000>; 904 regulator-min-microvolt = <1800000>;
874 regulator-max-microvolt = <1800000>; 905 regulator-max-microvolt = <1800000>;
875 enable-active-high; 906 enable-active-high;
876 gpio = <&gpio 61 0>; /* GPIO PH5 */ 907 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
877 }; 908 };
878 909
879 lcd_bl_en_reg: regulator@2 { 910 lcd_bl_en_reg: regulator@2 {
@@ -883,7 +914,7 @@
883 regulator-min-microvolt = <5000000>; 914 regulator-min-microvolt = <5000000>;
884 regulator-max-microvolt = <5000000>; 915 regulator-max-microvolt = <5000000>;
885 enable-active-high; 916 enable-active-high;
886 gpio = <&gpio 58 0>; /* GPIO PH2 */ 917 gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
887 }; 918 };
888 919
889 usb1_vbus_reg: regulator@3 { 920 usb1_vbus_reg: regulator@3 {
@@ -893,7 +924,7 @@
893 regulator-min-microvolt = <5000000>; 924 regulator-min-microvolt = <5000000>;
894 regulator-max-microvolt = <5000000>; 925 regulator-max-microvolt = <5000000>;
895 enable-active-high; 926 enable-active-high;
896 gpio = <&gpio 108 0>; /* GPIO PN4 */ 927 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
897 gpio-open-drain; 928 gpio-open-drain;
898 vin-supply = <&tps65090_dcdc1_reg>; 929 vin-supply = <&tps65090_dcdc1_reg>;
899 }; 930 };
@@ -905,7 +936,7 @@
905 regulator-min-microvolt = <5000000>; 936 regulator-min-microvolt = <5000000>;
906 regulator-max-microvolt = <5000000>; 937 regulator-max-microvolt = <5000000>;
907 enable-active-high; 938 enable-active-high;
908 gpio = <&gpio 86 0>; /* GPIO PK6 */ 939 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
909 gpio-open-drain; 940 gpio-open-drain;
910 vin-supply = <&tps65090_dcdc1_reg>; 941 vin-supply = <&tps65090_dcdc1_reg>;
911 }; 942 };
@@ -917,8 +948,32 @@
917 regulator-min-microvolt = <5000000>; 948 regulator-min-microvolt = <5000000>;
918 regulator-max-microvolt = <5000000>; 949 regulator-max-microvolt = <5000000>;
919 enable-active-high; 950 enable-active-high;
920 gpio = <&gpio 81 0>; /* GPIO PK1 */ 951 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
921 vin-supply = <&tps65090_dcdc1_reg>; 952 vin-supply = <&tps65090_dcdc1_reg>;
922 }; 953 };
923 }; 954 };
955
956 sound {
957 compatible = "nvidia,tegra-audio-rt5640-dalmore",
958 "nvidia,tegra-audio-rt5640";
959 nvidia,model = "NVIDIA Tegra Dalmore";
960
961 nvidia,audio-routing =
962 "Headphones", "HPOR",
963 "Headphones", "HPOL",
964 "Speakers", "SPORP",
965 "Speakers", "SPORN",
966 "Speakers", "SPOLP",
967 "Speakers", "SPOLN";
968
969 nvidia,i2s-controller = <&tegra_i2s1>;
970 nvidia,audio-codec = <&rt5640>;
971
972 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
973
974 clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
975 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
976 <&tegra_car TEGRA114_CLK_EXTERN1>;
977 clock-names = "pll_a", "pll_a_out0", "mclk";
978 };
924}; 979};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 6bbc8efae9c0..d5f8d3e0bde2 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra114.dtsi" 3#include "tegra114.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra114 Pluto evaluation board"; 6 model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 629415ffd8dc..abf6c40d28c6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,8 @@
1/include/ "skeleton.dtsi" 1#include <dt-bindings/clock/tegra114-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h>
4
5#include "skeleton.dtsi"
2 6
3/ { 7/ {
4 compatible = "nvidia,tegra114"; 8 compatible = "nvidia,tegra114";
@@ -19,19 +23,20 @@
19 <0x50042000 0x1000>, 23 <0x50042000 0x1000>,
20 <0x50044000 0x2000>, 24 <0x50044000 0x2000>,
21 <0x50046000 0x2000>; 25 <0x50046000 0x2000>;
22 interrupts = <1 9 0xf04>; 26 interrupts = <GIC_PPI 9
27 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
23 }; 28 };
24 29
25 timer@60005000 { 30 timer@60005000 {
26 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; 31 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
27 reg = <0x60005000 0x400>; 32 reg = <0x60005000 0x400>;
28 interrupts = <0 0 0x04 33 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
29 0 1 0x04 34 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
30 0 41 0x04 35 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
31 0 42 0x04 36 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
32 0 121 0x04 37 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
33 0 122 0x04>; 38 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&tegra_car 5>; 39 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
35 }; 40 };
36 41
37 tegra_car: clock { 42 tegra_car: clock {
@@ -43,39 +48,39 @@
43 apbdma: dma { 48 apbdma: dma {
44 compatible = "nvidia,tegra114-apbdma"; 49 compatible = "nvidia,tegra114-apbdma";
45 reg = <0x6000a000 0x1400>; 50 reg = <0x6000a000 0x1400>;
46 interrupts = <0 104 0x04 51 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
47 0 105 0x04 52 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
48 0 106 0x04 53 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
49 0 107 0x04 54 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
50 0 108 0x04 55 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
51 0 109 0x04 56 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
52 0 110 0x04 57 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
53 0 111 0x04 58 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
54 0 112 0x04 59 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
55 0 113 0x04 60 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
56 0 114 0x04 61 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
57 0 115 0x04 62 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
58 0 116 0x04 63 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
59 0 117 0x04 64 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
60 0 118 0x04 65 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
61 0 119 0x04 66 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
62 0 128 0x04 67 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
63 0 129 0x04 68 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
64 0 130 0x04 69 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
65 0 131 0x04 70 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
66 0 132 0x04 71 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
67 0 133 0x04 72 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
68 0 134 0x04 73 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
69 0 135 0x04 74 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
70 0 136 0x04 75 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
71 0 137 0x04 76 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
72 0 138 0x04 77 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
73 0 139 0x04 78 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
74 0 140 0x04 79 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
75 0 141 0x04 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
76 0 142 0x04 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
77 0 143 0x04>; 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&tegra_car 34>; 83 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
79 }; 84 };
80 85
81 ahb: ahb { 86 ahb: ahb {
@@ -86,14 +91,14 @@
86 gpio: gpio { 91 gpio: gpio {
87 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 92 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
88 reg = <0x6000d000 0x1000>; 93 reg = <0x6000d000 0x1000>;
89 interrupts = <0 32 0x04 94 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
90 0 33 0x04 95 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
91 0 34 0x04 96 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
92 0 35 0x04 97 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
93 0 55 0x04 98 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
94 0 87 0x04 99 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
95 0 89 0x04 100 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
96 0 125 0x04>; 101 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
97 #gpio-cells = <2>; 102 #gpio-cells = <2>;
98 gpio-controller; 103 gpio-controller;
99 #interrupt-cells = <2>; 104 #interrupt-cells = <2>;
@@ -118,57 +123,57 @@
118 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 123 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
119 reg = <0x70006000 0x40>; 124 reg = <0x70006000 0x40>;
120 reg-shift = <2>; 125 reg-shift = <2>;
121 interrupts = <0 36 0x04>; 126 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
122 nvidia,dma-request-selector = <&apbdma 8>; 127 nvidia,dma-request-selector = <&apbdma 8>;
123 status = "disabled"; 128 status = "disabled";
124 clocks = <&tegra_car 6>; 129 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
125 }; 130 };
126 131
127 uartb: serial@70006040 { 132 uartb: serial@70006040 {
128 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 133 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
129 reg = <0x70006040 0x40>; 134 reg = <0x70006040 0x40>;
130 reg-shift = <2>; 135 reg-shift = <2>;
131 interrupts = <0 37 0x04>; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
132 nvidia,dma-request-selector = <&apbdma 9>; 137 nvidia,dma-request-selector = <&apbdma 9>;
133 status = "disabled"; 138 status = "disabled";
134 clocks = <&tegra_car 192>; 139 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
135 }; 140 };
136 141
137 uartc: serial@70006200 { 142 uartc: serial@70006200 {
138 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 143 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
139 reg = <0x70006200 0x100>; 144 reg = <0x70006200 0x100>;
140 reg-shift = <2>; 145 reg-shift = <2>;
141 interrupts = <0 46 0x04>; 146 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
142 nvidia,dma-request-selector = <&apbdma 10>; 147 nvidia,dma-request-selector = <&apbdma 10>;
143 status = "disabled"; 148 status = "disabled";
144 clocks = <&tegra_car 55>; 149 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
145 }; 150 };
146 151
147 uartd: serial@70006300 { 152 uartd: serial@70006300 {
148 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 153 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
149 reg = <0x70006300 0x100>; 154 reg = <0x70006300 0x100>;
150 reg-shift = <2>; 155 reg-shift = <2>;
151 interrupts = <0 90 0x04>; 156 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
152 nvidia,dma-request-selector = <&apbdma 19>; 157 nvidia,dma-request-selector = <&apbdma 19>;
153 status = "disabled"; 158 status = "disabled";
154 clocks = <&tegra_car 65>; 159 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
155 }; 160 };
156 161
157 pwm: pwm { 162 pwm: pwm {
158 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 163 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
159 reg = <0x7000a000 0x100>; 164 reg = <0x7000a000 0x100>;
160 #pwm-cells = <2>; 165 #pwm-cells = <2>;
161 clocks = <&tegra_car 17>; 166 clocks = <&tegra_car TEGRA114_CLK_PWM>;
162 status = "disabled"; 167 status = "disabled";
163 }; 168 };
164 169
165 i2c@7000c000 { 170 i2c@7000c000 {
166 compatible = "nvidia,tegra114-i2c"; 171 compatible = "nvidia,tegra114-i2c";
167 reg = <0x7000c000 0x100>; 172 reg = <0x7000c000 0x100>;
168 interrupts = <0 38 0x04>; 173 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>; 174 #address-cells = <1>;
170 #size-cells = <0>; 175 #size-cells = <0>;
171 clocks = <&tegra_car 12>; 176 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
172 clock-names = "div-clk"; 177 clock-names = "div-clk";
173 status = "disabled"; 178 status = "disabled";
174 }; 179 };
@@ -176,10 +181,10 @@
176 i2c@7000c400 { 181 i2c@7000c400 {
177 compatible = "nvidia,tegra114-i2c"; 182 compatible = "nvidia,tegra114-i2c";
178 reg = <0x7000c400 0x100>; 183 reg = <0x7000c400 0x100>;
179 interrupts = <0 84 0x04>; 184 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
180 #address-cells = <1>; 185 #address-cells = <1>;
181 #size-cells = <0>; 186 #size-cells = <0>;
182 clocks = <&tegra_car 54>; 187 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
183 clock-names = "div-clk"; 188 clock-names = "div-clk";
184 status = "disabled"; 189 status = "disabled";
185 }; 190 };
@@ -187,10 +192,10 @@
187 i2c@7000c500 { 192 i2c@7000c500 {
188 compatible = "nvidia,tegra114-i2c"; 193 compatible = "nvidia,tegra114-i2c";
189 reg = <0x7000c500 0x100>; 194 reg = <0x7000c500 0x100>;
190 interrupts = <0 92 0x04>; 195 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
191 #address-cells = <1>; 196 #address-cells = <1>;
192 #size-cells = <0>; 197 #size-cells = <0>;
193 clocks = <&tegra_car 67>; 198 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
194 clock-names = "div-clk"; 199 clock-names = "div-clk";
195 status = "disabled"; 200 status = "disabled";
196 }; 201 };
@@ -198,10 +203,10 @@
198 i2c@7000c700 { 203 i2c@7000c700 {
199 compatible = "nvidia,tegra114-i2c"; 204 compatible = "nvidia,tegra114-i2c";
200 reg = <0x7000c700 0x100>; 205 reg = <0x7000c700 0x100>;
201 interrupts = <0 120 0x04>; 206 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
202 #address-cells = <1>; 207 #address-cells = <1>;
203 #size-cells = <0>; 208 #size-cells = <0>;
204 clocks = <&tegra_car 103>; 209 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
205 clock-names = "div-clk"; 210 clock-names = "div-clk";
206 status = "disabled"; 211 status = "disabled";
207 }; 212 };
@@ -209,10 +214,10 @@
209 i2c@7000d000 { 214 i2c@7000d000 {
210 compatible = "nvidia,tegra114-i2c"; 215 compatible = "nvidia,tegra114-i2c";
211 reg = <0x7000d000 0x100>; 216 reg = <0x7000d000 0x100>;
212 interrupts = <0 53 0x04>; 217 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
213 #address-cells = <1>; 218 #address-cells = <1>;
214 #size-cells = <0>; 219 #size-cells = <0>;
215 clocks = <&tegra_car 47>; 220 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
216 clock-names = "div-clk"; 221 clock-names = "div-clk";
217 status = "disabled"; 222 status = "disabled";
218 }; 223 };
@@ -220,11 +225,11 @@
220 spi@7000d400 { 225 spi@7000d400 {
221 compatible = "nvidia,tegra114-spi"; 226 compatible = "nvidia,tegra114-spi";
222 reg = <0x7000d400 0x200>; 227 reg = <0x7000d400 0x200>;
223 interrupts = <0 59 0x04>; 228 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
224 nvidia,dma-request-selector = <&apbdma 15>; 229 nvidia,dma-request-selector = <&apbdma 15>;
225 #address-cells = <1>; 230 #address-cells = <1>;
226 #size-cells = <0>; 231 #size-cells = <0>;
227 clocks = <&tegra_car 41>; 232 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
228 clock-names = "spi"; 233 clock-names = "spi";
229 status = "disabled"; 234 status = "disabled";
230 }; 235 };
@@ -232,11 +237,11 @@
232 spi@7000d600 { 237 spi@7000d600 {
233 compatible = "nvidia,tegra114-spi"; 238 compatible = "nvidia,tegra114-spi";
234 reg = <0x7000d600 0x200>; 239 reg = <0x7000d600 0x200>;
235 interrupts = <0 82 0x04>; 240 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
236 nvidia,dma-request-selector = <&apbdma 16>; 241 nvidia,dma-request-selector = <&apbdma 16>;
237 #address-cells = <1>; 242 #address-cells = <1>;
238 #size-cells = <0>; 243 #size-cells = <0>;
239 clocks = <&tegra_car 44>; 244 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
240 clock-names = "spi"; 245 clock-names = "spi";
241 status = "disabled"; 246 status = "disabled";
242 }; 247 };
@@ -244,11 +249,11 @@
244 spi@7000d800 { 249 spi@7000d800 {
245 compatible = "nvidia,tegra114-spi"; 250 compatible = "nvidia,tegra114-spi";
246 reg = <0x7000d800 0x200>; 251 reg = <0x7000d800 0x200>;
247 interrupts = <0 83 0x04>; 252 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
248 nvidia,dma-request-selector = <&apbdma 17>; 253 nvidia,dma-request-selector = <&apbdma 17>;
249 #address-cells = <1>; 254 #address-cells = <1>;
250 #size-cells = <0>; 255 #size-cells = <0>;
251 clocks = <&tegra_car 46>; 256 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
252 clock-names = "spi"; 257 clock-names = "spi";
253 status = "disabled"; 258 status = "disabled";
254 }; 259 };
@@ -256,11 +261,11 @@
256 spi@7000da00 { 261 spi@7000da00 {
257 compatible = "nvidia,tegra114-spi"; 262 compatible = "nvidia,tegra114-spi";
258 reg = <0x7000da00 0x200>; 263 reg = <0x7000da00 0x200>;
259 interrupts = <0 93 0x04>; 264 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
260 nvidia,dma-request-selector = <&apbdma 18>; 265 nvidia,dma-request-selector = <&apbdma 18>;
261 #address-cells = <1>; 266 #address-cells = <1>;
262 #size-cells = <0>; 267 #size-cells = <0>;
263 clocks = <&tegra_car 68>; 268 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
264 clock-names = "spi"; 269 clock-names = "spi";
265 status = "disabled"; 270 status = "disabled";
266 }; 271 };
@@ -268,11 +273,11 @@
268 spi@7000dc00 { 273 spi@7000dc00 {
269 compatible = "nvidia,tegra114-spi"; 274 compatible = "nvidia,tegra114-spi";
270 reg = <0x7000dc00 0x200>; 275 reg = <0x7000dc00 0x200>;
271 interrupts = <0 94 0x04>; 276 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
272 nvidia,dma-request-selector = <&apbdma 27>; 277 nvidia,dma-request-selector = <&apbdma 27>;
273 #address-cells = <1>; 278 #address-cells = <1>;
274 #size-cells = <0>; 279 #size-cells = <0>;
275 clocks = <&tegra_car 104>; 280 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
276 clock-names = "spi"; 281 clock-names = "spi";
277 status = "disabled"; 282 status = "disabled";
278 }; 283 };
@@ -280,11 +285,11 @@
280 spi@7000de00 { 285 spi@7000de00 {
281 compatible = "nvidia,tegra114-spi"; 286 compatible = "nvidia,tegra114-spi";
282 reg = <0x7000de00 0x200>; 287 reg = <0x7000de00 0x200>;
283 interrupts = <0 79 0x04>; 288 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
284 nvidia,dma-request-selector = <&apbdma 28>; 289 nvidia,dma-request-selector = <&apbdma 28>;
285 #address-cells = <1>; 290 #address-cells = <1>;
286 #size-cells = <0>; 291 #size-cells = <0>;
287 clocks = <&tegra_car 105>; 292 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
288 clock-names = "spi"; 293 clock-names = "spi";
289 status = "disabled"; 294 status = "disabled";
290 }; 295 };
@@ -292,22 +297,22 @@
292 rtc { 297 rtc {
293 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 298 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
294 reg = <0x7000e000 0x100>; 299 reg = <0x7000e000 0x100>;
295 interrupts = <0 2 0x04>; 300 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&tegra_car 4>; 301 clocks = <&tegra_car TEGRA114_CLK_RTC>;
297 }; 302 };
298 303
299 kbc { 304 kbc {
300 compatible = "nvidia,tegra114-kbc"; 305 compatible = "nvidia,tegra114-kbc";
301 reg = <0x7000e200 0x100>; 306 reg = <0x7000e200 0x100>;
302 interrupts = <0 85 0x04>; 307 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&tegra_car 36>; 308 clocks = <&tegra_car TEGRA114_CLK_KBC>;
304 status = "disabled"; 309 status = "disabled";
305 }; 310 };
306 311
307 pmc { 312 pmc {
308 compatible = "nvidia,tegra114-pmc"; 313 compatible = "nvidia,tegra114-pmc";
309 reg = <0x7000e400 0x400>; 314 reg = <0x7000e400 0x400>;
310 clocks = <&tegra_car 261>, <&clk32k_in>; 315 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
311 clock-names = "pclk", "clk32k_in"; 316 clock-names = "pclk", "clk32k_in";
312 }; 317 };
313 318
@@ -322,35 +327,106 @@
322 nvidia,ahb = <&ahb>; 327 nvidia,ahb = <&ahb>;
323 }; 328 };
324 329
330 ahub {
331 compatible = "nvidia,tegra114-ahub";
332 reg = <0x70080000 0x200>,
333 <0x70080200 0x100>,
334 <0x70081000 0x200>;
335 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
336 nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
337 <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
338 <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
339 <&apbdma 29>;
340 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
341 <&tegra_car TEGRA114_CLK_APBIF>,
342 <&tegra_car TEGRA114_CLK_I2S0>,
343 <&tegra_car TEGRA114_CLK_I2S1>,
344 <&tegra_car TEGRA114_CLK_I2S2>,
345 <&tegra_car TEGRA114_CLK_I2S3>,
346 <&tegra_car TEGRA114_CLK_I2S4>,
347 <&tegra_car TEGRA114_CLK_DAM0>,
348 <&tegra_car TEGRA114_CLK_DAM1>,
349 <&tegra_car TEGRA114_CLK_DAM2>,
350 <&tegra_car TEGRA114_CLK_SPDIF_IN>,
351 <&tegra_car TEGRA114_CLK_AMX>,
352 <&tegra_car TEGRA114_CLK_ADX>;
353 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
354 "i2s3", "i2s4", "dam0", "dam1", "dam2",
355 "spdif_in", "amx", "adx";
356 ranges;
357 #address-cells = <1>;
358 #size-cells = <1>;
359
360 tegra_i2s0: i2s@70080300 {
361 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
362 reg = <0x70080300 0x100>;
363 nvidia,ahub-cif-ids = <4 4>;
364 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
365 status = "disabled";
366 };
367
368 tegra_i2s1: i2s@70080400 {
369 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
370 reg = <0x70080400 0x100>;
371 nvidia,ahub-cif-ids = <5 5>;
372 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
373 status = "disabled";
374 };
375
376 tegra_i2s2: i2s@70080500 {
377 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
378 reg = <0x70080500 0x100>;
379 nvidia,ahub-cif-ids = <6 6>;
380 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
381 status = "disabled";
382 };
383
384 tegra_i2s3: i2s@70080600 {
385 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
386 reg = <0x70080600 0x100>;
387 nvidia,ahub-cif-ids = <7 7>;
388 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
389 status = "disabled";
390 };
391
392 tegra_i2s4: i2s@70080700 {
393 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
394 reg = <0x70080700 0x100>;
395 nvidia,ahub-cif-ids = <8 8>;
396 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
397 status = "disabled";
398 };
399 };
400
325 sdhci@78000000 { 401 sdhci@78000000 {
326 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 402 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
327 reg = <0x78000000 0x200>; 403 reg = <0x78000000 0x200>;
328 interrupts = <0 14 0x04>; 404 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&tegra_car 14>; 405 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
330 status = "disable"; 406 status = "disable";
331 }; 407 };
332 408
333 sdhci@78000200 { 409 sdhci@78000200 {
334 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 410 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
335 reg = <0x78000200 0x200>; 411 reg = <0x78000200 0x200>;
336 interrupts = <0 15 0x04>; 412 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&tegra_car 9>; 413 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
338 status = "disable"; 414 status = "disable";
339 }; 415 };
340 416
341 sdhci@78000400 { 417 sdhci@78000400 {
342 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 418 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
343 reg = <0x78000400 0x200>; 419 reg = <0x78000400 0x200>;
344 interrupts = <0 19 0x04>; 420 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&tegra_car 69>; 421 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
346 status = "disable"; 422 status = "disable";
347 }; 423 };
348 424
349 sdhci@78000600 { 425 sdhci@78000600 {
350 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 426 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
351 reg = <0x78000600 0x200>; 427 reg = <0x78000600 0x200>;
352 interrupts = <0 31 0x04>; 428 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&tegra_car 15>; 429 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
354 status = "disable"; 430 status = "disable";
355 }; 431 };
356 432
@@ -385,9 +461,14 @@
385 461
386 timer { 462 timer {
387 compatible = "arm,armv7-timer"; 463 compatible = "arm,armv7-timer";
388 interrupts = <1 13 0xf08>, 464 interrupts =
389 <1 14 0xf08>, 465 <GIC_PPI 13
390 <1 11 0xf08>, 466 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
391 <1 10 0xf08>; 467 <GIC_PPI 14
468 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
469 <GIC_PPI 11
470 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
471 <GIC_PPI 10
472 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
392 }; 473 };
393}; 474};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index a573b94b7c93..2fcb3f2ca160 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -1,4 +1,4 @@
1/include/ "tegra20.dtsi" 1#include "tegra20.dtsi"
2 2
3/ { 3/ {
4 model = "Toradex Colibri T20 512MB"; 4 model = "Toradex Colibri T20 512MB";
@@ -14,7 +14,8 @@
14 pll-supply = <&hdmi_pll_reg>; 14 pll-supply = <&hdmi_pll_reg>;
15 15
16 nvidia,ddc-i2c-bus = <&i2c_ddc>; 16 nvidia,ddc-i2c-bus = <&i2c_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 17 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
18 GPIO_ACTIVE_HIGH>;
18 }; 19 };
19 }; 20 };
20 21
@@ -217,7 +218,7 @@
217 pmic: tps6586x@34 { 218 pmic: tps6586x@34 {
218 compatible = "ti,tps6586x"; 219 compatible = "ti,tps6586x";
219 reg = <0x34>; 220 reg = <0x34>;
220 interrupts = <0 86 0x4>; 221 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
221 222
222 ti,system-power-controller; 223 ti,system-power-controller;
223 224
@@ -443,17 +444,25 @@
443 444
444 ac97: ac97 { 445 ac97: ac97 {
445 status = "okay"; 446 status = "okay";
446 nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 447 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
447 nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */ 448 GPIO_ACTIVE_HIGH>;
449 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
450 GPIO_ACTIVE_HIGH>;
448 }; 451 };
449 452
450 usb@c5004000 { 453 usb@c5004000 {
451 status = "okay"; 454 status = "okay";
452 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 455 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
456 GPIO_ACTIVE_LOW>;
457 };
458
459 usb-phy@c5004000 {
460 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
461 GPIO_ACTIVE_LOW>;
453 }; 462 };
454 463
455 sdhci@c8000600 { 464 sdhci@c8000600 {
456 cd-gpios = <&gpio 23 1>; /* gpio PC7 */ 465 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
457 }; 466 };
458 467
459 clocks { 468 clocks {
@@ -483,7 +492,9 @@
483 492
484 nvidia,ac97-controller = <&ac97>; 493 nvidia,ac97-controller = <&ac97>;
485 494
486 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 495 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
496 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
497 <&tegra_car TEGRA20_CLK_CDEV1>;
487 clock-names = "pll_a", "pll_a_out0", "mclk"; 498 clock-names = "pll_a", "pll_a_out0", "mclk";
488 }; 499 };
489 500
@@ -510,7 +521,7 @@
510 enable-active-high; 521 enable-active-high;
511 regulator-boot-on; 522 regulator-boot-on;
512 regulator-always-on; 523 regulator-always-on;
513 gpio = <&gpio 217 0>; 524 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
514 }; 525 };
515 }; 526 };
516}; 527};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e7d5de4e00b9..d9f89cd879a7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20.dtsi" 3#include "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra20 Harmony evaluation board"; 6 model = "NVIDIA Tegra20 Harmony evaluation board";
@@ -18,7 +18,8 @@
18 pll-supply = <&hdmi_pll_reg>; 18 pll-supply = <&hdmi_pll_reg>;
19 19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
22 }; 23 };
23 }; 24 };
24 25
@@ -262,7 +263,7 @@
262 compatible = "wlf,wm8903"; 263 compatible = "wlf,wm8903";
263 reg = <0x1a>; 264 reg = <0x1a>;
264 interrupt-parent = <&gpio>; 265 interrupt-parent = <&gpio>;
265 interrupts = <187 0x04>; 266 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
266 267
267 gpio-controller; 268 gpio-controller;
268 #gpio-cells = <2>; 269 #gpio-cells = <2>;
@@ -290,7 +291,7 @@
290 pmic: tps6586x@34 { 291 pmic: tps6586x@34 {
291 compatible = "ti,tps6586x"; 292 compatible = "ti,tps6586x";
292 reg = <0x34>; 293 reg = <0x34>;
293 interrupts = <0 86 0x4>; 294 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
294 295
295 ti,system-power-controller; 296 ti,system-power-controller;
296 297
@@ -428,32 +429,43 @@
428 status = "okay"; 429 status = "okay";
429 }; 430 };
430 431
432 usb-phy@c5000000 {
433 status = "okay";
434 };
435
431 usb@c5004000 { 436 usb@c5004000 {
432 status = "okay"; 437 status = "okay";
433 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 438 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
439 GPIO_ACTIVE_LOW>;
440 };
441
442 usb-phy@c5004000 {
443 status = "okay";
444 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
445 GPIO_ACTIVE_LOW>;
434 }; 446 };
435 447
436 usb@c5008000 { 448 usb@c5008000 {
437 status = "okay"; 449 status = "okay";
438 }; 450 };
439 451
440 usb-phy@c5004400 { 452 usb-phy@c5008000 {
441 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 453 status = "okay";
442 }; 454 };
443 455
444 sdhci@c8000200 { 456 sdhci@c8000200 {
445 status = "okay"; 457 status = "okay";
446 cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 458 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
447 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 459 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
448 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 460 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
449 bus-width = <4>; 461 bus-width = <4>;
450 }; 462 };
451 463
452 sdhci@c8000600 { 464 sdhci@c8000600 {
453 status = "okay"; 465 status = "okay";
454 cd-gpios = <&gpio 58 1>; /* gpio PH2 */ 466 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
455 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 467 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
456 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 468 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
457 bus-width = <8>; 469 bus-width = <8>;
458 }; 470 };
459 471
@@ -475,7 +487,7 @@
475 487
476 power { 488 power {
477 label = "Power"; 489 label = "Power";
478 gpios = <&gpio 170 1>; /* gpio PV2, active low */ 490 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
479 linux,code = <116>; /* KEY_POWER */ 491 linux,code = <116>; /* KEY_POWER */
480 gpio-key,wakeup; 492 gpio-key,wakeup;
481 }; 493 };
@@ -618,7 +630,7 @@
618 regulator-name = "vdd_1v5"; 630 regulator-name = "vdd_1v5";
619 regulator-min-microvolt = <1500000>; 631 regulator-min-microvolt = <1500000>;
620 regulator-max-microvolt = <1500000>; 632 regulator-max-microvolt = <1500000>;
621 gpio = <&pmic 0 0>; 633 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
622 }; 634 };
623 635
624 regulator@2 { 636 regulator@2 {
@@ -627,7 +639,7 @@
627 regulator-name = "vdd_1v2"; 639 regulator-name = "vdd_1v2";
628 regulator-min-microvolt = <1200000>; 640 regulator-min-microvolt = <1200000>;
629 regulator-max-microvolt = <1200000>; 641 regulator-max-microvolt = <1200000>;
630 gpio = <&pmic 1 0>; 642 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
631 enable-active-high; 643 enable-active-high;
632 }; 644 };
633 645
@@ -637,7 +649,7 @@
637 regulator-name = "vdd_1v05"; 649 regulator-name = "vdd_1v05";
638 regulator-min-microvolt = <1050000>; 650 regulator-min-microvolt = <1050000>;
639 regulator-max-microvolt = <1050000>; 651 regulator-max-microvolt = <1050000>;
640 gpio = <&pmic 2 0>; 652 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
641 enable-active-high; 653 enable-active-high;
642 /* Hack until board-harmony-pcie.c is removed */ 654 /* Hack until board-harmony-pcie.c is removed */
643 status = "disabled"; 655 status = "disabled";
@@ -649,7 +661,7 @@
649 regulator-name = "vdd_pnl"; 661 regulator-name = "vdd_pnl";
650 regulator-min-microvolt = <2800000>; 662 regulator-min-microvolt = <2800000>;
651 regulator-max-microvolt = <2800000>; 663 regulator-max-microvolt = <2800000>;
652 gpio = <&gpio 22 0>; /* gpio PC6 */ 664 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
653 enable-active-high; 665 enable-active-high;
654 }; 666 };
655 667
@@ -659,7 +671,7 @@
659 regulator-name = "vdd_bl"; 671 regulator-name = "vdd_bl";
660 regulator-min-microvolt = <2800000>; 672 regulator-min-microvolt = <2800000>;
661 regulator-max-microvolt = <2800000>; 673 regulator-max-microvolt = <2800000>;
662 gpio = <&gpio 176 0>; /* gpio PW0 */ 674 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
663 enable-active-high; 675 enable-active-high;
664 }; 676 };
665 }; 677 };
@@ -682,12 +694,17 @@
682 nvidia,i2s-controller = <&tegra_i2s1>; 694 nvidia,i2s-controller = <&tegra_i2s1>;
683 nvidia,audio-codec = <&wm8903>; 695 nvidia,audio-codec = <&wm8903>;
684 696
685 nvidia,spkr-en-gpios = <&wm8903 2 0>; 697 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
686 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 698 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
687 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 699 GPIO_ACTIVE_HIGH>;
688 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 700 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
689 701 GPIO_ACTIVE_HIGH>;
690 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 702 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
703 GPIO_ACTIVE_HIGH>;
704
705 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
706 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
707 <&tegra_car TEGRA20_CLK_CDEV1>;
691 clock-names = "pll_a", "pll_a_out0", "mclk"; 708 clock-names = "pll_a", "pll_a_out0", "mclk";
692 }; 709 };
693}; 710};
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 52f1103907d7..f2222bd74eab 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20-colibri-512.dtsi" 3#include "tegra20-colibri-512.dtsi"
4 4
5/ { 5/ {
6 model = "Toradex Colibri T20 512MB on Iris"; 6 model = "Toradex Colibri T20 512MB on Iris";
@@ -38,13 +38,20 @@
38 38
39 usb@c5000000 { 39 usb@c5000000 {
40 status = "okay"; 40 status = "okay";
41 dr_mode = "otg"; 41 };
42
43 usb-phy@c5000000 {
44 status = "okay";
42 }; 45 };
43 46
44 usb@c5008000 { 47 usb@c5008000 {
45 status = "okay"; 48 status = "okay";
46 }; 49 };
47 50
51 usb-phy@c5008000 {
52 status = "okay";
53 };
54
48 serial@70006000 { 55 serial@70006000 {
49 status = "okay"; 56 status = "okay";
50 }; 57 };
@@ -73,7 +80,7 @@
73 regulator-max-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>;
74 regulator-boot-on; 81 regulator-boot-on;
75 regulator-always-on; 82 regulator-always-on;
76 gpio = <&gpio 178 0>; 83 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
77 }; 84 };
78 85
79 vcc_sd_reg: regulator@1 { 86 vcc_sd_reg: regulator@1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index ace23437da89..7580578903cf 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20-tamonten.dtsi" 3#include "tegra20-tamonten.dtsi"
4 4
5/ { 5/ {
6 model = "Avionic Design Medcom-Wide board"; 6 model = "Avionic Design Medcom-Wide board";
@@ -15,7 +15,7 @@
15 compatible = "wlf,wm8903"; 15 compatible = "wlf,wm8903";
16 reg = <0x1a>; 16 reg = <0x1a>;
17 interrupt-parent = <&gpio>; 17 interrupt-parent = <&gpio>;
18 interrupts = <187 0x04>; 18 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
19 19
20 gpio-controller; 20 gpio-controller;
21 #gpio-cells = <2>; 21 #gpio-cells = <2>;
@@ -56,10 +56,12 @@
56 nvidia,i2s-controller = <&tegra_i2s1>; 56 nvidia,i2s-controller = <&tegra_i2s1>;
57 nvidia,audio-codec = <&wm8903>; 57 nvidia,audio-codec = <&wm8903>;
58 58
59 nvidia,spkr-en-gpios = <&wm8903 2 0>; 59 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
60 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 60 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
61 61
62 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 62 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
63 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
64 <&tegra_car TEGRA20_CLK_CDEV1>;
63 clock-names = "pll_a", "pll_a_out0", "mclk"; 65 clock-names = "pll_a", "pll_a_out0", "mclk";
64 }; 66 };
65}; 67};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e3e0c9977df4..cfd12763b1b2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20.dtsi" 3#include "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "Toshiba AC100 / Dynabook AZ"; 6 model = "Toshiba AC100 / Dynabook AZ";
@@ -18,7 +18,8 @@
18 pll-supply = <&hdmi_pll_reg>; 18 pll-supply = <&hdmi_pll_reg>;
19 19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
22 }; 23 };
23 }; 24 };
24 25
@@ -270,13 +271,14 @@
270 nvec { 271 nvec {
271 compatible = "nvidia,nvec"; 272 compatible = "nvidia,nvec";
272 reg = <0x7000c500 0x100>; 273 reg = <0x7000c500 0x100>;
273 interrupts = <0 92 0x04>; 274 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>; 275 #address-cells = <1>;
275 #size-cells = <0>; 276 #size-cells = <0>;
276 clock-frequency = <80000>; 277 clock-frequency = <80000>;
277 request-gpios = <&gpio 170 0>; /* gpio PV2 */ 278 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
278 slave-addr = <138>; 279 slave-addr = <138>;
279 clocks = <&tegra_car 67>, <&tegra_car 124>; 280 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
281 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
280 clock-names = "div-clk", "fast-clk"; 282 clock-names = "div-clk", "fast-clk";
281 }; 283 };
282 284
@@ -287,7 +289,7 @@
287 pmic: tps6586x@34 { 289 pmic: tps6586x@34 {
288 compatible = "ti,tps6586x"; 290 compatible = "ti,tps6586x";
289 reg = <0x34>; 291 reg = <0x34>;
290 interrupts = <0 86 0x4>; 292 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
291 293
292 #gpio-cells = <2>; 294 #gpio-cells = <2>;
293 gpio-controller; 295 gpio-controller;
@@ -427,24 +429,35 @@
427 status = "okay"; 429 status = "okay";
428 }; 430 };
429 431
432 usb-phy@c5000000 {
433 status = "okay";
434 };
435
430 usb@c5004000 { 436 usb@c5004000 {
431 status = "okay"; 437 status = "okay";
432 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 438 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
439 GPIO_ACTIVE_LOW>;
440 };
441
442 usb-phy@c5004000 {
443 status = "okay";
444 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
445 GPIO_ACTIVE_LOW>;
433 }; 446 };
434 447
435 usb@c5008000 { 448 usb@c5008000 {
436 status = "okay"; 449 status = "okay";
437 }; 450 };
438 451
439 usb-phy@c5004400 { 452 usb-phy@c5008000 {
440 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 453 status = "okay";
441 }; 454 };
442 455
443 sdhci@c8000000 { 456 sdhci@c8000000 {
444 status = "okay"; 457 status = "okay";
445 cd-gpios = <&gpio 173 1>; /* gpio PV5 */ 458 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
446 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 459 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
447 power-gpios = <&gpio 169 0>; /* gpio PV1 */ 460 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
448 bus-width = <4>; 461 bus-width = <4>;
449 }; 462 };
450 463
@@ -472,7 +485,7 @@
472 485
473 power { 486 power {
474 label = "Power"; 487 label = "Power";
475 gpios = <&gpio 79 1>; /* gpio PJ7, active low */ 488 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
476 linux,code = <116>; /* KEY_POWER */ 489 linux,code = <116>; /* KEY_POWER */
477 gpio-key,wakeup; 490 gpio-key,wakeup;
478 }; 491 };
@@ -483,7 +496,7 @@
483 496
484 wifi { 497 wifi {
485 label = "wifi-led"; 498 label = "wifi-led";
486 gpios = <&gpio 24 0>; /* gpio PD0 */ 499 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
487 linux,default-trigger = "rfkill0"; 500 linux,default-trigger = "rfkill0";
488 }; 501 };
489 }; 502 };
@@ -520,9 +533,12 @@
520 533
521 nvidia,audio-codec = <&alc5632>; 534 nvidia,audio-codec = <&alc5632>;
522 nvidia,i2s-controller = <&tegra_i2s1>; 535 nvidia,i2s-controller = <&tegra_i2s1>;
523 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 536 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
537 GPIO_ACTIVE_HIGH>;
524 538
525 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 539 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
540 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
541 <&tegra_car TEGRA20_CLK_CDEV1>;
526 clock-names = "pll_a", "pll_a_out0", "mclk"; 542 clock-names = "pll_a", "pll_a_out0", "mclk";
527 }; 543 };
528}; 544};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 1a17cc30bb9d..d7a358a6a647 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20-tamonten.dtsi" 3#include "tegra20-tamonten.dtsi"
4 4
5/ { 5/ {
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
@@ -17,7 +17,7 @@
17 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
18 reg = <0x1a>; 18 reg = <0x1a>;
19 interrupt-parent = <&gpio>; 19 interrupt-parent = <&gpio>;
20 interrupts = <187 0x04>; 20 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
21 21
22 gpio-controller; 22 gpio-controller;
23 #gpio-cells = <2>; 23 #gpio-cells = <2>;
@@ -50,10 +50,12 @@
50 nvidia,i2s-controller = <&tegra_i2s1>; 50 nvidia,i2s-controller = <&tegra_i2s1>;
51 nvidia,audio-codec = <&wm8903>; 51 nvidia,audio-codec = <&wm8903>;
52 52
53 nvidia,spkr-en-gpios = <&wm8903 2 0>; 53 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
55 55
56 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 56 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
57 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
58 <&tegra_car TEGRA20_CLK_CDEV1>;
57 clock-names = "pll_a", "pll_a_out0", "mclk"; 59 clock-names = "pll_a", "pll_a_out0", "mclk";
58 }; 60 };
59}; 61};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index cee4c34010fe..ab177b406b78 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20.dtsi" 3#include "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Seaboard"; 6 model = "NVIDIA Seaboard";
@@ -18,7 +18,8 @@
18 pll-supply = <&hdmi_pll_reg>; 18 pll-supply = <&hdmi_pll_reg>;
19 19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
22 }; 23 };
23 }; 24 };
24 25
@@ -313,7 +314,7 @@
313 compatible = "wlf,wm8903"; 314 compatible = "wlf,wm8903";
314 reg = <0x1a>; 315 reg = <0x1a>;
315 interrupt-parent = <&gpio>; 316 interrupt-parent = <&gpio>;
316 interrupts = <187 0x04>; 317 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
317 318
318 gpio-controller; 319 gpio-controller;
319 #gpio-cells = <2>; 320 #gpio-cells = <2>;
@@ -328,14 +329,14 @@
328 compatible = "isil,isl29018"; 329 compatible = "isil,isl29018";
329 reg = <0x44>; 330 reg = <0x44>;
330 interrupt-parent = <&gpio>; 331 interrupt-parent = <&gpio>;
331 interrupts = <202 0x04>; /* GPIO PZ2 */ 332 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
332 }; 333 };
333 334
334 gyrometer@68 { 335 gyrometer@68 {
335 compatible = "invn,mpu3050"; 336 compatible = "invn,mpu3050";
336 reg = <0x68>; 337 reg = <0x68>;
337 interrupt-parent = <&gpio>; 338 interrupt-parent = <&gpio>;
338 interrupts = <204 0x04>; /* gpio PZ4 */ 339 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
339 }; 340 };
340 }; 341 };
341 342
@@ -388,7 +389,7 @@
388 pmic: tps6586x@34 { 389 pmic: tps6586x@34 {
389 compatible = "ti,tps6586x"; 390 compatible = "ti,tps6586x";
390 reg = <0x34>; 391 reg = <0x34>;
391 interrupts = <0 86 0x4>; 392 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
392 393
393 ti,system-power-controller; 394 ti,system-power-controller;
394 395
@@ -511,7 +512,7 @@
511 compatible = "ak,ak8975"; 512 compatible = "ak,ak8975";
512 reg = <0xc>; 513 reg = <0xc>;
513 interrupt-parent = <&gpio>; 514 interrupt-parent = <&gpio>;
514 interrupts = <109 0x04>; /* gpio PN5 */ 515 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
515 }; 516 };
516 }; 517 };
517 518
@@ -565,35 +566,48 @@
565 566
566 usb@c5000000 { 567 usb@c5000000 {
567 status = "okay"; 568 status = "okay";
568 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ 569 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
570 dr_mode = "otg";
571 };
572
573 usb-phy@c5000000 {
574 status = "okay";
575 vbus-supply = <&vbus_reg>;
569 dr_mode = "otg"; 576 dr_mode = "otg";
570 }; 577 };
571 578
572 usb@c5004000 { 579 usb@c5004000 {
573 status = "okay"; 580 status = "okay";
574 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 581 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
582 GPIO_ACTIVE_LOW>;
583 };
584
585 usb-phy@c5004000 {
586 status = "okay";
587 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
588 GPIO_ACTIVE_LOW>;
575 }; 589 };
576 590
577 usb@c5008000 { 591 usb@c5008000 {
578 status = "okay"; 592 status = "okay";
579 }; 593 };
580 594
581 usb-phy@c5004400 { 595 usb-phy@c5008000 {
582 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 596 status = "okay";
583 }; 597 };
584 598
585 sdhci@c8000000 { 599 sdhci@c8000000 {
586 status = "okay"; 600 status = "okay";
587 power-gpios = <&gpio 86 0>; /* gpio PK6 */ 601 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
588 bus-width = <4>; 602 bus-width = <4>;
589 keep-power-in-suspend; 603 keep-power-in-suspend;
590 }; 604 };
591 605
592 sdhci@c8000400 { 606 sdhci@c8000400 {
593 status = "okay"; 607 status = "okay";
594 cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 608 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
595 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 609 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
596 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 610 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
597 bus-width = <4>; 611 bus-width = <4>;
598 }; 612 };
599 613
@@ -621,14 +635,14 @@
621 635
622 power { 636 power {
623 label = "Power"; 637 label = "Power";
624 gpios = <&gpio 170 1>; /* gpio PV2, active low */ 638 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
625 linux,code = <116>; /* KEY_POWER */ 639 linux,code = <116>; /* KEY_POWER */
626 gpio-key,wakeup; 640 gpio-key,wakeup;
627 }; 641 };
628 642
629 lid { 643 lid {
630 label = "Lid"; 644 label = "Lid";
631 gpios = <&gpio 23 0>; /* gpio PC7 */ 645 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
632 linux,input-type = <5>; /* EV_SW */ 646 linux,input-type = <5>; /* EV_SW */
633 linux,code = <0>; /* SW_LID */ 647 linux,code = <0>; /* SW_LID */
634 debounce-interval = <1>; 648 debounce-interval = <1>;
@@ -795,7 +809,7 @@
795 regulator-name = "vdd_1v5"; 809 regulator-name = "vdd_1v5";
796 regulator-min-microvolt = <1500000>; 810 regulator-min-microvolt = <1500000>;
797 regulator-max-microvolt = <1500000>; 811 regulator-max-microvolt = <1500000>;
798 gpio = <&pmic 0 0>; 812 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
799 }; 813 };
800 814
801 regulator@2 { 815 regulator@2 {
@@ -804,9 +818,18 @@
804 regulator-name = "vdd_1v2"; 818 regulator-name = "vdd_1v2";
805 regulator-min-microvolt = <1200000>; 819 regulator-min-microvolt = <1200000>;
806 regulator-max-microvolt = <1200000>; 820 regulator-max-microvolt = <1200000>;
807 gpio = <&pmic 1 0>; 821 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
808 enable-active-high; 822 enable-active-high;
809 }; 823 };
824
825 vbus_reg: regulator@3 {
826 compatible = "regulator-fixed";
827 reg = <3>;
828 regulator-name = "vdd_vbus_wup1";
829 regulator-min-microvolt = <5000000>;
830 regulator-max-microvolt = <5000000>;
831 gpio = <&gpio 24 0>; /* PD0 */
832 };
810 }; 833 };
811 834
812 sound { 835 sound {
@@ -827,10 +850,12 @@
827 nvidia,i2s-controller = <&tegra_i2s1>; 850 nvidia,i2s-controller = <&tegra_i2s1>;
828 nvidia,audio-codec = <&wm8903>; 851 nvidia,audio-codec = <&wm8903>;
829 852
830 nvidia,spkr-en-gpios = <&wm8903 2 0>; 853 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
831 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ 854 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
832 855
833 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 856 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
857 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
858 <&tegra_car TEGRA20_CLK_CDEV1>;
834 clock-names = "pll_a", "pll_a_out0", "mclk"; 859 clock-names = "pll_a", "pll_a_out0", "mclk";
835 }; 860 };
836}; 861};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 50b3ec16b93a..c54faae7cfb3 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -1,4 +1,4 @@
1/include/ "tegra20.dtsi" 1#include "tegra20.dtsi"
2 2
3/ { 3/ {
4 model = "Avionic Design Tamonten SOM"; 4 model = "Avionic Design Tamonten SOM";
@@ -14,7 +14,8 @@
14 pll-supply = <&hdmi_pll_reg>; 14 pll-supply = <&hdmi_pll_reg>;
15 15
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 17 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
18 GPIO_ACTIVE_HIGH>;
18 }; 19 };
19 }; 20 };
20 21
@@ -321,7 +322,7 @@
321 pmic: tps6586x@34 { 322 pmic: tps6586x@34 {
322 compatible = "ti,tps6586x"; 323 compatible = "ti,tps6586x";
323 reg = <0x34>; 324 reg = <0x34>;
324 interrupts = <0 86 0x4>; 325 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
325 326
326 ti,system-power-controller; 327 ti,system-power-controller;
327 328
@@ -470,9 +471,13 @@
470 status = "okay"; 471 status = "okay";
471 }; 472 };
472 473
474 usb-phy@c5008000 {
475 status = "okay";
476 };
477
473 sdhci@c8000600 { 478 sdhci@c8000600 {
474 cd-gpios = <&gpio 58 1>; /* gpio PH2 */ 479 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
475 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 480 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
476 bus-width = <4>; 481 bus-width = <4>;
477 status = "okay"; 482 status = "okay";
478 }; 483 };
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 742f0b38d21d..c572c43751b1 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20-tamonten.dtsi" 3#include "tegra20-tamonten.dtsi"
4 4
5/ { 5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
@@ -17,7 +17,7 @@
17 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
18 reg = <0x1a>; 18 reg = <0x1a>;
19 interrupt-parent = <&gpio>; 19 interrupt-parent = <&gpio>;
20 interrupts = <187 0x04>; 20 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
21 21
22 gpio-controller; 22 gpio-controller;
23 #gpio-cells = <2>; 23 #gpio-cells = <2>;
@@ -50,10 +50,13 @@
50 nvidia,i2s-controller = <&tegra_i2s1>; 50 nvidia,i2s-controller = <&tegra_i2s1>;
51 nvidia,audio-codec = <&wm8903>; 51 nvidia,audio-codec = <&wm8903>;
52 52
53 nvidia,spkr-en-gpios = <&wm8903 2 0>; 53 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
55 GPIO_ACTIVE_HIGH>;
55 56
56 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 57 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
59 <&tegra_car TEGRA20_CLK_CDEV1>;
57 clock-names = "pll_a", "pll_a_out0", "mclk"; 60 clock-names = "pll_a", "pll_a_out0", "mclk";
58 }; 61 };
59}; 62};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9cc78a15d739..170159910455 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20.dtsi" 3#include "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "Compulab TrimSlice board"; 6 model = "Compulab TrimSlice board";
@@ -18,7 +18,8 @@
18 pll-supply = <&hdmi_pll_reg>; 18 pll-supply = <&hdmi_pll_reg>;
19 19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
22 }; 23 };
23 }; 24 };
24 25
@@ -311,20 +312,32 @@
311 312
312 usb@c5000000 { 313 usb@c5000000 {
313 status = "okay"; 314 status = "okay";
314 nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ 315 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
316 };
317
318 usb-phy@c5000000 {
319 status = "okay";
320 vbus-supply = <&vbus_reg>;
315 }; 321 };
316 322
317 usb@c5004000 { 323 usb@c5004000 {
318 status = "okay"; 324 status = "okay";
319 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 325 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
326 GPIO_ACTIVE_LOW>;
327 };
328
329 usb-phy@c5004000 {
330 status = "okay";
331 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
332 GPIO_ACTIVE_LOW>;
320 }; 333 };
321 334
322 usb@c5008000 { 335 usb@c5008000 {
323 status = "okay"; 336 status = "okay";
324 }; 337 };
325 338
326 usb-phy@c5004400 { 339 usb-phy@c5008000 {
327 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 340 status = "okay";
328 }; 341 };
329 342
330 sdhci@c8000000 { 343 sdhci@c8000000 {
@@ -334,8 +347,8 @@
334 347
335 sdhci@c8000600 { 348 sdhci@c8000600 {
336 status = "okay"; 349 status = "okay";
337 cd-gpios = <&gpio 121 1>; /* gpio PP1 */ 350 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
338 wp-gpios = <&gpio 122 0>; /* gpio PP2 */ 351 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
339 bus-width = <4>; 352 bus-width = <4>;
340 }; 353 };
341 354
@@ -357,7 +370,7 @@
357 370
358 power { 371 power {
359 label = "Power"; 372 label = "Power";
360 gpios = <&gpio 190 1>; /* gpio PX6, active low */ 373 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
361 linux,code = <116>; /* KEY_POWER */ 374 linux,code = <116>; /* KEY_POWER */
362 gpio-key,wakeup; 375 gpio-key,wakeup;
363 }; 376 };
@@ -365,7 +378,7 @@
365 378
366 poweroff { 379 poweroff {
367 compatible = "gpio-poweroff"; 380 compatible = "gpio-poweroff";
368 gpios = <&gpio 191 1>; /* gpio PX7, active low */ 381 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
369 }; 382 };
370 383
371 regulators { 384 regulators {
@@ -390,6 +403,15 @@
390 regulator-max-microvolt = <1800000>; 403 regulator-max-microvolt = <1800000>;
391 regulator-always-on; 404 regulator-always-on;
392 }; 405 };
406
407 vbus_reg: regulator@2 {
408 compatible = "regulator-fixed";
409 reg = <2>;
410 regulator-name = "usb1_vbus";
411 regulator-min-microvolt = <5000000>;
412 regulator-max-microvolt = <5000000>;
413 gpio = <&gpio 170 0>; /* PV2 */
414 };
393 }; 415 };
394 416
395 sound { 417 sound {
@@ -397,7 +419,9 @@
397 nvidia,i2s-controller = <&tegra_i2s1>; 419 nvidia,i2s-controller = <&tegra_i2s1>;
398 nvidia,audio-codec = <&codec>; 420 nvidia,audio-codec = <&codec>;
399 421
400 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 422 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
423 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
424 <&tegra_car TEGRA20_CLK_CDEV1>;
401 clock-names = "pll_a", "pll_a_out0", "mclk"; 425 clock-names = "pll_a", "pll_a_out0", "mclk";
402 }; 426 };
403}; 427};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index dd38f1f03834..7f8c28d1121f 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20.dtsi" 3#include "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra20 Ventana evaluation board"; 6 model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -18,7 +18,8 @@
18 pll-supply = <&hdmi_pll_reg>; 18 pll-supply = <&hdmi_pll_reg>;
19 19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
22 }; 23 };
23 }; 24 };
24 25
@@ -310,7 +311,7 @@
310 compatible = "wlf,wm8903"; 311 compatible = "wlf,wm8903";
311 reg = <0x1a>; 312 reg = <0x1a>;
312 interrupt-parent = <&gpio>; 313 interrupt-parent = <&gpio>;
313 interrupts = <187 0x04>; 314 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
314 315
315 gpio-controller; 316 gpio-controller;
316 #gpio-cells = <2>; 317 #gpio-cells = <2>;
@@ -325,7 +326,7 @@
325 compatible = "isil,isl29018"; 326 compatible = "isil,isl29018";
326 reg = <0x44>; 327 reg = <0x44>;
327 interrupt-parent = <&gpio>; 328 interrupt-parent = <&gpio>;
328 interrupts = <202 0x04>; /*gpio PZ2 */ 329 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
329 }; 330 };
330 }; 331 };
331 332
@@ -371,7 +372,7 @@
371 pmic: tps6586x@34 { 372 pmic: tps6586x@34 {
372 compatible = "ti,tps6586x"; 373 compatible = "ti,tps6586x";
373 reg = <0x34>; 374 reg = <0x34>;
374 interrupts = <0 86 0x4>; 375 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
375 376
376 ti,system-power-controller; 377 ti,system-power-controller;
377 378
@@ -505,31 +506,42 @@
505 status = "okay"; 506 status = "okay";
506 }; 507 };
507 508
509 usb-phy@c5000000 {
510 status = "okay";
511 };
512
508 usb@c5004000 { 513 usb@c5004000 {
509 status = "okay"; 514 status = "okay";
510 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 515 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
516 GPIO_ACTIVE_LOW>;
517 };
518
519 usb-phy@c5004000 {
520 status = "okay";
521 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
522 GPIO_ACTIVE_LOW>;
511 }; 523 };
512 524
513 usb@c5008000 { 525 usb@c5008000 {
514 status = "okay"; 526 status = "okay";
515 }; 527 };
516 528
517 usb-phy@c5004400 { 529 usb-phy@c5008000 {
518 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 530 status = "okay";
519 }; 531 };
520 532
521 sdhci@c8000000 { 533 sdhci@c8000000 {
522 status = "okay"; 534 status = "okay";
523 power-gpios = <&gpio 86 0>; /* gpio PK6 */ 535 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
524 bus-width = <4>; 536 bus-width = <4>;
525 keep-power-in-suspend; 537 keep-power-in-suspend;
526 }; 538 };
527 539
528 sdhci@c8000400 { 540 sdhci@c8000400 {
529 status = "okay"; 541 status = "okay";
530 cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 542 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
531 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 543 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
532 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 544 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
533 bus-width = <4>; 545 bus-width = <4>;
534 }; 546 };
535 547
@@ -557,7 +569,7 @@
557 569
558 power { 570 power {
559 label = "Power"; 571 label = "Power";
560 gpios = <&gpio 170 1>; /* gpio PV2, active low */ 572 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
561 linux,code = <116>; /* KEY_POWER */ 573 linux,code = <116>; /* KEY_POWER */
562 gpio-key,wakeup; 574 gpio-key,wakeup;
563 }; 575 };
@@ -583,7 +595,7 @@
583 regulator-name = "vdd_1v5"; 595 regulator-name = "vdd_1v5";
584 regulator-min-microvolt = <1500000>; 596 regulator-min-microvolt = <1500000>;
585 regulator-max-microvolt = <1500000>; 597 regulator-max-microvolt = <1500000>;
586 gpio = <&pmic 0 0>; 598 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
587 }; 599 };
588 600
589 regulator@2 { 601 regulator@2 {
@@ -592,7 +604,7 @@
592 regulator-name = "vdd_1v2"; 604 regulator-name = "vdd_1v2";
593 regulator-min-microvolt = <1200000>; 605 regulator-min-microvolt = <1200000>;
594 regulator-max-microvolt = <1200000>; 606 regulator-max-microvolt = <1200000>;
595 gpio = <&pmic 1 0>; 607 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
596 enable-active-high; 608 enable-active-high;
597 }; 609 };
598 610
@@ -602,7 +614,7 @@
602 regulator-name = "vdd_pnl"; 614 regulator-name = "vdd_pnl";
603 regulator-min-microvolt = <2800000>; 615 regulator-min-microvolt = <2800000>;
604 regulator-max-microvolt = <2800000>; 616 regulator-max-microvolt = <2800000>;
605 gpio = <&gpio 22 0>; /* gpio PC6 */ 617 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
606 enable-active-high; 618 enable-active-high;
607 }; 619 };
608 620
@@ -612,7 +624,7 @@
612 regulator-name = "vdd_bl"; 624 regulator-name = "vdd_bl";
613 regulator-min-microvolt = <2800000>; 625 regulator-min-microvolt = <2800000>;
614 regulator-max-microvolt = <2800000>; 626 regulator-max-microvolt = <2800000>;
615 gpio = <&gpio 176 0>; /* gpio PW0 */ 627 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
616 enable-active-high; 628 enable-active-high;
617 }; 629 };
618 }; 630 };
@@ -635,12 +647,16 @@
635 nvidia,i2s-controller = <&tegra_i2s1>; 647 nvidia,i2s-controller = <&tegra_i2s1>;
636 nvidia,audio-codec = <&wm8903>; 648 nvidia,audio-codec = <&wm8903>;
637 649
638 nvidia,spkr-en-gpios = <&wm8903 2 0>; 650 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
639 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 651 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
640 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ 652 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
641 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 653 GPIO_ACTIVE_HIGH>;
654 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
655 GPIO_ACTIVE_HIGH>;
642 656
643 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 657 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
658 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
659 <&tegra_car TEGRA20_CLK_CDEV1>;
644 clock-names = "pll_a", "pll_a_out0", "mclk"; 660 clock-names = "pll_a", "pll_a_out0", "mclk";
645 }; 661 };
646}; 662};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d2567f83aaff..ea078ab8edeb 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra20.dtsi" 3#include "tegra20.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra20 Whistler evaluation board"; 6 model = "NVIDIA Tegra20 Whistler evaluation board";
@@ -18,7 +18,8 @@
18 pll-supply = <&hdmi_pll_reg>; 18 pll-supply = <&hdmi_pll_reg>;
19 19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
22 }; 23 };
23 }; 24 };
24 25
@@ -281,7 +282,7 @@
281 max8907@3c { 282 max8907@3c {
282 compatible = "maxim,max8907"; 283 compatible = "maxim,max8907";
283 reg = <0x3c>; 284 reg = <0x3c>;
284 interrupts = <0 86 0x4>; 285 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
285 286
286 maxim,system-power-controller; 287 maxim,system-power-controller;
287 288
@@ -508,18 +509,28 @@
508 509
509 usb@c5000000 { 510 usb@c5000000 {
510 status = "okay"; 511 status = "okay";
511 nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ 512 nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
513 };
514
515 usb-phy@c5000000 {
516 status = "okay";
517 vbus-supply = <&vbus1_reg>;
512 }; 518 };
513 519
514 usb@c5008000 { 520 usb@c5008000 {
515 status = "okay"; 521 status = "okay";
516 nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ 522 nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
523 };
524
525 usb-phy@c5008000 {
526 status = "okay";
527 vbus-supply = <&vbus3_reg>;
517 }; 528 };
518 529
519 sdhci@c8000400 { 530 sdhci@c8000400 {
520 status = "okay"; 531 status = "okay";
521 cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 532 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
522 wp-gpios = <&gpio 173 0>; /* gpio PV5 */ 533 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
523 bus-width = <8>; 534 bus-width = <8>;
524 }; 535 };
525 536
@@ -568,6 +579,24 @@
568 regulator-max-microvolt = <5000000>; 579 regulator-max-microvolt = <5000000>;
569 regulator-always-on; 580 regulator-always-on;
570 }; 581 };
582
583 vbus1_reg: regulator@2 {
584 compatible = "regulator-fixed";
585 reg = <2>;
586 regulator-name = "vbus1";
587 regulator-min-microvolt = <5000000>;
588 regulator-max-microvolt = <5000000>;
589 gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
590 };
591
592 vbus3_reg: regulator@3 {
593 compatible = "regulator-fixed";
594 reg = <3>;
595 regulator-name = "vbus3";
596 regulator-min-microvolt = <5000000>;
597 regulator-max-microvolt = <5000000>;
598 gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
599 };
571 }; 600 };
572 601
573 sound { 602 sound {
@@ -584,7 +613,9 @@
584 nvidia,i2s-controller = <&tegra_i2s1>; 613 nvidia,i2s-controller = <&tegra_i2s1>;
585 nvidia,audio-codec = <&codec>; 614 nvidia,audio-codec = <&codec>;
586 615
587 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 616 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
617 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
618 <&tegra_car TEGRA20_CLK_CDEV1>;
588 clock-names = "pll_a", "pll_a_out0", "mclk"; 619 clock-names = "pll_a", "pll_a_out0", "mclk";
589 }; 620 };
590}; 621};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 56a91106041b..9653fd8288d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,4 +1,8 @@
1/include/ "skeleton.dtsi" 1#include <dt-bindings/clock/tegra20-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h>
4
5#include "skeleton.dtsi"
2 6
3/ { 7/ {
4 compatible = "nvidia,tegra20"; 8 compatible = "nvidia,tegra20";
@@ -15,9 +19,9 @@
15 host1x { 19 host1x {
16 compatible = "nvidia,tegra20-host1x", "simple-bus"; 20 compatible = "nvidia,tegra20-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>; 21 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */ 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
19 0 67 0x04>; /* mpcore general */ 23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
20 clocks = <&tegra_car 28>; 24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
21 25
22 #address-cells = <1>; 26 #address-cells = <1>;
23 #size-cells = <1>; 27 #size-cells = <1>;
@@ -27,49 +31,50 @@
27 mpe { 31 mpe {
28 compatible = "nvidia,tegra20-mpe"; 32 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>; 33 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>; 34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&tegra_car 60>; 35 clocks = <&tegra_car TEGRA20_CLK_MPE>;
32 }; 36 };
33 37
34 vi { 38 vi {
35 compatible = "nvidia,tegra20-vi"; 39 compatible = "nvidia,tegra20-vi";
36 reg = <0x54080000 0x00040000>; 40 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>; 41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&tegra_car 100>; 42 clocks = <&tegra_car TEGRA20_CLK_VI>;
39 }; 43 };
40 44
41 epp { 45 epp {
42 compatible = "nvidia,tegra20-epp"; 46 compatible = "nvidia,tegra20-epp";
43 reg = <0x540c0000 0x00040000>; 47 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>; 48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
45 clocks = <&tegra_car 19>; 49 clocks = <&tegra_car TEGRA20_CLK_EPP>;
46 }; 50 };
47 51
48 isp { 52 isp {
49 compatible = "nvidia,tegra20-isp"; 53 compatible = "nvidia,tegra20-isp";
50 reg = <0x54100000 0x00040000>; 54 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>; 55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
52 clocks = <&tegra_car 23>; 56 clocks = <&tegra_car TEGRA20_CLK_ISP>;
53 }; 57 };
54 58
55 gr2d { 59 gr2d {
56 compatible = "nvidia,tegra20-gr2d"; 60 compatible = "nvidia,tegra20-gr2d";
57 reg = <0x54140000 0x00040000>; 61 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>; 62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
59 clocks = <&tegra_car 21>; 63 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
60 }; 64 };
61 65
62 gr3d { 66 gr3d {
63 compatible = "nvidia,tegra20-gr3d"; 67 compatible = "nvidia,tegra20-gr3d";
64 reg = <0x54180000 0x00040000>; 68 reg = <0x54180000 0x00040000>;
65 clocks = <&tegra_car 24>; 69 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
66 }; 70 };
67 71
68 dc@54200000 { 72 dc@54200000 {
69 compatible = "nvidia,tegra20-dc"; 73 compatible = "nvidia,tegra20-dc";
70 reg = <0x54200000 0x00040000>; 74 reg = <0x54200000 0x00040000>;
71 interrupts = <0 73 0x04>; 75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&tegra_car 27>, <&tegra_car 121>; 76 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
77 <&tegra_car TEGRA20_CLK_PLL_P>;
73 clock-names = "disp1", "parent"; 78 clock-names = "disp1", "parent";
74 79
75 rgb { 80 rgb {
@@ -80,8 +85,9 @@
80 dc@54240000 { 85 dc@54240000 {
81 compatible = "nvidia,tegra20-dc"; 86 compatible = "nvidia,tegra20-dc";
82 reg = <0x54240000 0x00040000>; 87 reg = <0x54240000 0x00040000>;
83 interrupts = <0 74 0x04>; 88 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&tegra_car 26>, <&tegra_car 121>; 89 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
90 <&tegra_car TEGRA20_CLK_PLL_P>;
85 clock-names = "disp2", "parent"; 91 clock-names = "disp2", "parent";
86 92
87 rgb { 93 rgb {
@@ -92,8 +98,9 @@
92 hdmi { 98 hdmi {
93 compatible = "nvidia,tegra20-hdmi"; 99 compatible = "nvidia,tegra20-hdmi";
94 reg = <0x54280000 0x00040000>; 100 reg = <0x54280000 0x00040000>;
95 interrupts = <0 75 0x04>; 101 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&tegra_car 51>, <&tegra_car 117>; 102 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
103 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
97 clock-names = "hdmi", "parent"; 104 clock-names = "hdmi", "parent";
98 status = "disabled"; 105 status = "disabled";
99 }; 106 };
@@ -101,15 +108,15 @@
101 tvo { 108 tvo {
102 compatible = "nvidia,tegra20-tvo"; 109 compatible = "nvidia,tegra20-tvo";
103 reg = <0x542c0000 0x00040000>; 110 reg = <0x542c0000 0x00040000>;
104 interrupts = <0 76 0x04>; 111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&tegra_car 102>; 112 clocks = <&tegra_car TEGRA20_CLK_TVO>;
106 status = "disabled"; 113 status = "disabled";
107 }; 114 };
108 115
109 dsi { 116 dsi {
110 compatible = "nvidia,tegra20-dsi"; 117 compatible = "nvidia,tegra20-dsi";
111 reg = <0x54300000 0x00040000>; 118 reg = <0x54300000 0x00040000>;
112 clocks = <&tegra_car 48>; 119 clocks = <&tegra_car TEGRA20_CLK_DSI>;
113 status = "disabled"; 120 status = "disabled";
114 }; 121 };
115 }; 122 };
@@ -117,8 +124,9 @@
117 timer@50004600 { 124 timer@50004600 {
118 compatible = "arm,cortex-a9-twd-timer"; 125 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x50040600 0x20>; 126 reg = <0x50040600 0x20>;
120 interrupts = <1 13 0x304>; 127 interrupts = <GIC_PPI 13
121 clocks = <&tegra_car 132>; 128 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
129 clocks = <&tegra_car TEGRA20_CLK_TWD>;
122 }; 130 };
123 131
124 intc: interrupt-controller { 132 intc: interrupt-controller {
@@ -141,11 +149,11 @@
141 timer@60005000 { 149 timer@60005000 {
142 compatible = "nvidia,tegra20-timer"; 150 compatible = "nvidia,tegra20-timer";
143 reg = <0x60005000 0x60>; 151 reg = <0x60005000 0x60>;
144 interrupts = <0 0 0x04 152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
145 0 1 0x04 153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
146 0 41 0x04 154 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
147 0 42 0x04>; 155 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&tegra_car 5>; 156 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
149 }; 157 };
150 158
151 tegra_car: clock { 159 tegra_car: clock {
@@ -157,23 +165,23 @@
157 apbdma: dma { 165 apbdma: dma {
158 compatible = "nvidia,tegra20-apbdma"; 166 compatible = "nvidia,tegra20-apbdma";
159 reg = <0x6000a000 0x1200>; 167 reg = <0x6000a000 0x1200>;
160 interrupts = <0 104 0x04 168 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
161 0 105 0x04 169 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
162 0 106 0x04 170 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
163 0 107 0x04 171 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
164 0 108 0x04 172 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
165 0 109 0x04 173 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
166 0 110 0x04 174 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
167 0 111 0x04 175 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
168 0 112 0x04 176 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
169 0 113 0x04 177 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
170 0 114 0x04 178 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
171 0 115 0x04 179 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
172 0 116 0x04 180 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
173 0 117 0x04 181 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
174 0 118 0x04 182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
175 0 119 0x04>; 183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&tegra_car 34>; 184 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
177 }; 185 };
178 186
179 ahb { 187 ahb {
@@ -184,13 +192,13 @@
184 gpio: gpio { 192 gpio: gpio {
185 compatible = "nvidia,tegra20-gpio"; 193 compatible = "nvidia,tegra20-gpio";
186 reg = <0x6000d000 0x1000>; 194 reg = <0x6000d000 0x1000>;
187 interrupts = <0 32 0x04 195 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
188 0 33 0x04 196 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
189 0 34 0x04 197 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
190 0 35 0x04 198 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
191 0 55 0x04 199 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
192 0 87 0x04 200 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
193 0 89 0x04>; 201 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
194 #gpio-cells = <2>; 202 #gpio-cells = <2>;
195 gpio-controller; 203 gpio-controller;
196 #interrupt-cells = <2>; 204 #interrupt-cells = <2>;
@@ -213,27 +221,27 @@
213 tegra_ac97: ac97 { 221 tegra_ac97: ac97 {
214 compatible = "nvidia,tegra20-ac97"; 222 compatible = "nvidia,tegra20-ac97";
215 reg = <0x70002000 0x200>; 223 reg = <0x70002000 0x200>;
216 interrupts = <0 81 0x04>; 224 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
217 nvidia,dma-request-selector = <&apbdma 12>; 225 nvidia,dma-request-selector = <&apbdma 12>;
218 clocks = <&tegra_car 3>; 226 clocks = <&tegra_car TEGRA20_CLK_AC97>;
219 status = "disabled"; 227 status = "disabled";
220 }; 228 };
221 229
222 tegra_i2s1: i2s@70002800 { 230 tegra_i2s1: i2s@70002800 {
223 compatible = "nvidia,tegra20-i2s"; 231 compatible = "nvidia,tegra20-i2s";
224 reg = <0x70002800 0x200>; 232 reg = <0x70002800 0x200>;
225 interrupts = <0 13 0x04>; 233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
226 nvidia,dma-request-selector = <&apbdma 2>; 234 nvidia,dma-request-selector = <&apbdma 2>;
227 clocks = <&tegra_car 11>; 235 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
228 status = "disabled"; 236 status = "disabled";
229 }; 237 };
230 238
231 tegra_i2s2: i2s@70002a00 { 239 tegra_i2s2: i2s@70002a00 {
232 compatible = "nvidia,tegra20-i2s"; 240 compatible = "nvidia,tegra20-i2s";
233 reg = <0x70002a00 0x200>; 241 reg = <0x70002a00 0x200>;
234 interrupts = <0 3 0x04>; 242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
235 nvidia,dma-request-selector = <&apbdma 1>; 243 nvidia,dma-request-selector = <&apbdma 1>;
236 clocks = <&tegra_car 18>; 244 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
237 status = "disabled"; 245 status = "disabled";
238 }; 246 };
239 247
@@ -248,9 +256,9 @@
248 compatible = "nvidia,tegra20-uart"; 256 compatible = "nvidia,tegra20-uart";
249 reg = <0x70006000 0x40>; 257 reg = <0x70006000 0x40>;
250 reg-shift = <2>; 258 reg-shift = <2>;
251 interrupts = <0 36 0x04>; 259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
252 nvidia,dma-request-selector = <&apbdma 8>; 260 nvidia,dma-request-selector = <&apbdma 8>;
253 clocks = <&tegra_car 6>; 261 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
254 status = "disabled"; 262 status = "disabled";
255 }; 263 };
256 264
@@ -258,9 +266,9 @@
258 compatible = "nvidia,tegra20-uart"; 266 compatible = "nvidia,tegra20-uart";
259 reg = <0x70006040 0x40>; 267 reg = <0x70006040 0x40>;
260 reg-shift = <2>; 268 reg-shift = <2>;
261 interrupts = <0 37 0x04>; 269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
262 nvidia,dma-request-selector = <&apbdma 9>; 270 nvidia,dma-request-selector = <&apbdma 9>;
263 clocks = <&tegra_car 96>; 271 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
264 status = "disabled"; 272 status = "disabled";
265 }; 273 };
266 274
@@ -268,9 +276,9 @@
268 compatible = "nvidia,tegra20-uart"; 276 compatible = "nvidia,tegra20-uart";
269 reg = <0x70006200 0x100>; 277 reg = <0x70006200 0x100>;
270 reg-shift = <2>; 278 reg-shift = <2>;
271 interrupts = <0 46 0x04>; 279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
272 nvidia,dma-request-selector = <&apbdma 10>; 280 nvidia,dma-request-selector = <&apbdma 10>;
273 clocks = <&tegra_car 55>; 281 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
274 status = "disabled"; 282 status = "disabled";
275 }; 283 };
276 284
@@ -278,9 +286,9 @@
278 compatible = "nvidia,tegra20-uart"; 286 compatible = "nvidia,tegra20-uart";
279 reg = <0x70006300 0x100>; 287 reg = <0x70006300 0x100>;
280 reg-shift = <2>; 288 reg-shift = <2>;
281 interrupts = <0 90 0x04>; 289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
282 nvidia,dma-request-selector = <&apbdma 19>; 290 nvidia,dma-request-selector = <&apbdma 19>;
283 clocks = <&tegra_car 65>; 291 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
284 status = "disabled"; 292 status = "disabled";
285 }; 293 };
286 294
@@ -288,9 +296,9 @@
288 compatible = "nvidia,tegra20-uart"; 296 compatible = "nvidia,tegra20-uart";
289 reg = <0x70006400 0x100>; 297 reg = <0x70006400 0x100>;
290 reg-shift = <2>; 298 reg-shift = <2>;
291 interrupts = <0 91 0x04>; 299 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
292 nvidia,dma-request-selector = <&apbdma 20>; 300 nvidia,dma-request-selector = <&apbdma 20>;
293 clocks = <&tegra_car 66>; 301 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
294 status = "disabled"; 302 status = "disabled";
295 }; 303 };
296 304
@@ -298,24 +306,25 @@
298 compatible = "nvidia,tegra20-pwm"; 306 compatible = "nvidia,tegra20-pwm";
299 reg = <0x7000a000 0x100>; 307 reg = <0x7000a000 0x100>;
300 #pwm-cells = <2>; 308 #pwm-cells = <2>;
301 clocks = <&tegra_car 17>; 309 clocks = <&tegra_car TEGRA20_CLK_PWM>;
302 status = "disabled"; 310 status = "disabled";
303 }; 311 };
304 312
305 rtc { 313 rtc {
306 compatible = "nvidia,tegra20-rtc"; 314 compatible = "nvidia,tegra20-rtc";
307 reg = <0x7000e000 0x100>; 315 reg = <0x7000e000 0x100>;
308 interrupts = <0 2 0x04>; 316 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&tegra_car 4>; 317 clocks = <&tegra_car TEGRA20_CLK_RTC>;
310 }; 318 };
311 319
312 i2c@7000c000 { 320 i2c@7000c000 {
313 compatible = "nvidia,tegra20-i2c"; 321 compatible = "nvidia,tegra20-i2c";
314 reg = <0x7000c000 0x100>; 322 reg = <0x7000c000 0x100>;
315 interrupts = <0 38 0x04>; 323 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>; 324 #address-cells = <1>;
317 #size-cells = <0>; 325 #size-cells = <0>;
318 clocks = <&tegra_car 12>, <&tegra_car 124>; 326 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
327 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
319 clock-names = "div-clk", "fast-clk"; 328 clock-names = "div-clk", "fast-clk";
320 status = "disabled"; 329 status = "disabled";
321 }; 330 };
@@ -323,21 +332,22 @@
323 spi@7000c380 { 332 spi@7000c380 {
324 compatible = "nvidia,tegra20-sflash"; 333 compatible = "nvidia,tegra20-sflash";
325 reg = <0x7000c380 0x80>; 334 reg = <0x7000c380 0x80>;
326 interrupts = <0 39 0x04>; 335 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
327 nvidia,dma-request-selector = <&apbdma 11>; 336 nvidia,dma-request-selector = <&apbdma 11>;
328 #address-cells = <1>; 337 #address-cells = <1>;
329 #size-cells = <0>; 338 #size-cells = <0>;
330 clocks = <&tegra_car 43>; 339 clocks = <&tegra_car TEGRA20_CLK_SPI>;
331 status = "disabled"; 340 status = "disabled";
332 }; 341 };
333 342
334 i2c@7000c400 { 343 i2c@7000c400 {
335 compatible = "nvidia,tegra20-i2c"; 344 compatible = "nvidia,tegra20-i2c";
336 reg = <0x7000c400 0x100>; 345 reg = <0x7000c400 0x100>;
337 interrupts = <0 84 0x04>; 346 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>; 347 #address-cells = <1>;
339 #size-cells = <0>; 348 #size-cells = <0>;
340 clocks = <&tegra_car 54>, <&tegra_car 124>; 349 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
350 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
341 clock-names = "div-clk", "fast-clk"; 351 clock-names = "div-clk", "fast-clk";
342 status = "disabled"; 352 status = "disabled";
343 }; 353 };
@@ -345,10 +355,11 @@
345 i2c@7000c500 { 355 i2c@7000c500 {
346 compatible = "nvidia,tegra20-i2c"; 356 compatible = "nvidia,tegra20-i2c";
347 reg = <0x7000c500 0x100>; 357 reg = <0x7000c500 0x100>;
348 interrupts = <0 92 0x04>; 358 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>; 359 #address-cells = <1>;
350 #size-cells = <0>; 360 #size-cells = <0>;
351 clocks = <&tegra_car 67>, <&tegra_car 124>; 361 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
362 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
352 clock-names = "div-clk", "fast-clk"; 363 clock-names = "div-clk", "fast-clk";
353 status = "disabled"; 364 status = "disabled";
354 }; 365 };
@@ -356,10 +367,11 @@
356 i2c@7000d000 { 367 i2c@7000d000 {
357 compatible = "nvidia,tegra20-i2c-dvc"; 368 compatible = "nvidia,tegra20-i2c-dvc";
358 reg = <0x7000d000 0x200>; 369 reg = <0x7000d000 0x200>;
359 interrupts = <0 53 0x04>; 370 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>; 371 #address-cells = <1>;
361 #size-cells = <0>; 372 #size-cells = <0>;
362 clocks = <&tegra_car 47>, <&tegra_car 124>; 373 clocks = <&tegra_car TEGRA20_CLK_DVC>,
374 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
363 clock-names = "div-clk", "fast-clk"; 375 clock-names = "div-clk", "fast-clk";
364 status = "disabled"; 376 status = "disabled";
365 }; 377 };
@@ -367,59 +379,59 @@
367 spi@7000d400 { 379 spi@7000d400 {
368 compatible = "nvidia,tegra20-slink"; 380 compatible = "nvidia,tegra20-slink";
369 reg = <0x7000d400 0x200>; 381 reg = <0x7000d400 0x200>;
370 interrupts = <0 59 0x04>; 382 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
371 nvidia,dma-request-selector = <&apbdma 15>; 383 nvidia,dma-request-selector = <&apbdma 15>;
372 #address-cells = <1>; 384 #address-cells = <1>;
373 #size-cells = <0>; 385 #size-cells = <0>;
374 clocks = <&tegra_car 41>; 386 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
375 status = "disabled"; 387 status = "disabled";
376 }; 388 };
377 389
378 spi@7000d600 { 390 spi@7000d600 {
379 compatible = "nvidia,tegra20-slink"; 391 compatible = "nvidia,tegra20-slink";
380 reg = <0x7000d600 0x200>; 392 reg = <0x7000d600 0x200>;
381 interrupts = <0 82 0x04>; 393 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
382 nvidia,dma-request-selector = <&apbdma 16>; 394 nvidia,dma-request-selector = <&apbdma 16>;
383 #address-cells = <1>; 395 #address-cells = <1>;
384 #size-cells = <0>; 396 #size-cells = <0>;
385 clocks = <&tegra_car 44>; 397 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
386 status = "disabled"; 398 status = "disabled";
387 }; 399 };
388 400
389 spi@7000d800 { 401 spi@7000d800 {
390 compatible = "nvidia,tegra20-slink"; 402 compatible = "nvidia,tegra20-slink";
391 reg = <0x7000d800 0x200>; 403 reg = <0x7000d800 0x200>;
392 interrupts = <0 83 0x04>; 404 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
393 nvidia,dma-request-selector = <&apbdma 17>; 405 nvidia,dma-request-selector = <&apbdma 17>;
394 #address-cells = <1>; 406 #address-cells = <1>;
395 #size-cells = <0>; 407 #size-cells = <0>;
396 clocks = <&tegra_car 46>; 408 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
397 status = "disabled"; 409 status = "disabled";
398 }; 410 };
399 411
400 spi@7000da00 { 412 spi@7000da00 {
401 compatible = "nvidia,tegra20-slink"; 413 compatible = "nvidia,tegra20-slink";
402 reg = <0x7000da00 0x200>; 414 reg = <0x7000da00 0x200>;
403 interrupts = <0 93 0x04>; 415 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
404 nvidia,dma-request-selector = <&apbdma 18>; 416 nvidia,dma-request-selector = <&apbdma 18>;
405 #address-cells = <1>; 417 #address-cells = <1>;
406 #size-cells = <0>; 418 #size-cells = <0>;
407 clocks = <&tegra_car 68>; 419 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
408 status = "disabled"; 420 status = "disabled";
409 }; 421 };
410 422
411 kbc { 423 kbc {
412 compatible = "nvidia,tegra20-kbc"; 424 compatible = "nvidia,tegra20-kbc";
413 reg = <0x7000e200 0x100>; 425 reg = <0x7000e200 0x100>;
414 interrupts = <0 85 0x04>; 426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&tegra_car 36>; 427 clocks = <&tegra_car TEGRA20_CLK_KBC>;
416 status = "disabled"; 428 status = "disabled";
417 }; 429 };
418 430
419 pmc { 431 pmc {
420 compatible = "nvidia,tegra20-pmc"; 432 compatible = "nvidia,tegra20-pmc";
421 reg = <0x7000e400 0x400>; 433 reg = <0x7000e400 0x400>;
422 clocks = <&tegra_car 110>, <&clk32k_in>; 434 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
423 clock-names = "pclk", "clk32k_in"; 435 clock-names = "pclk", "clk32k_in";
424 }; 436 };
425 437
@@ -427,7 +439,7 @@
427 compatible = "nvidia,tegra20-mc"; 439 compatible = "nvidia,tegra20-mc";
428 reg = <0x7000f000 0x024 440 reg = <0x7000f000 0x024
429 0x7000f03c 0x3c4>; 441 0x7000f03c 0x3c4>;
430 interrupts = <0 77 0x04>; 442 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
431 }; 443 };
432 444
433 iommu { 445 iommu {
@@ -446,89 +458,114 @@
446 usb@c5000000 { 458 usb@c5000000 {
447 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 459 compatible = "nvidia,tegra20-ehci", "usb-ehci";
448 reg = <0xc5000000 0x4000>; 460 reg = <0xc5000000 0x4000>;
449 interrupts = <0 20 0x04>; 461 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
450 phy_type = "utmi"; 462 phy_type = "utmi";
451 nvidia,has-legacy-mode; 463 nvidia,has-legacy-mode;
452 clocks = <&tegra_car 22>; 464 clocks = <&tegra_car TEGRA20_CLK_USBD>;
453 nvidia,needs-double-reset; 465 nvidia,needs-double-reset;
454 nvidia,phy = <&phy1>; 466 nvidia,phy = <&phy1>;
455 status = "disabled"; 467 status = "disabled";
456 }; 468 };
457 469
458 phy1: usb-phy@c5000400 { 470 phy1: usb-phy@c5000000 {
459 compatible = "nvidia,tegra20-usb-phy"; 471 compatible = "nvidia,tegra20-usb-phy";
460 reg = <0xc5000400 0x3c00>; 472 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
461 phy_type = "utmi"; 473 phy_type = "utmi";
474 clocks = <&tegra_car TEGRA20_CLK_USBD>,
475 <&tegra_car TEGRA20_CLK_PLL_U>,
476 <&tegra_car TEGRA20_CLK_CLK_M>,
477 <&tegra_car TEGRA20_CLK_USBD>;
478 clock-names = "reg", "pll_u", "timer", "utmi-pads";
462 nvidia,has-legacy-mode; 479 nvidia,has-legacy-mode;
463 clocks = <&tegra_car 22>, <&tegra_car 127>; 480 hssync_start_delay = <9>;
464 clock-names = "phy", "pll_u"; 481 idle_wait_delay = <17>;
482 elastic_limit = <16>;
483 term_range_adj = <6>;
484 xcvr_setup = <9>;
485 xcvr_lsfslew = <1>;
486 xcvr_lsrslew = <1>;
487 status = "disabled";
465 }; 488 };
466 489
467 usb@c5004000 { 490 usb@c5004000 {
468 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 491 compatible = "nvidia,tegra20-ehci", "usb-ehci";
469 reg = <0xc5004000 0x4000>; 492 reg = <0xc5004000 0x4000>;
470 interrupts = <0 21 0x04>; 493 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
471 phy_type = "ulpi"; 494 phy_type = "ulpi";
472 clocks = <&tegra_car 58>; 495 clocks = <&tegra_car TEGRA20_CLK_USB2>;
473 nvidia,phy = <&phy2>; 496 nvidia,phy = <&phy2>;
474 status = "disabled"; 497 status = "disabled";
475 }; 498 };
476 499
477 phy2: usb-phy@c5004400 { 500 phy2: usb-phy@c5004000 {
478 compatible = "nvidia,tegra20-usb-phy"; 501 compatible = "nvidia,tegra20-usb-phy";
479 reg = <0xc5004400 0x3c00>; 502 reg = <0xc5004000 0x4000>;
480 phy_type = "ulpi"; 503 phy_type = "ulpi";
481 clocks = <&tegra_car 93>, <&tegra_car 127>; 504 clocks = <&tegra_car TEGRA20_CLK_USB2>,
482 clock-names = "phy", "pll_u"; 505 <&tegra_car TEGRA20_CLK_PLL_U>,
506 <&tegra_car TEGRA20_CLK_CDEV2>;
507 clock-names = "reg", "pll_u", "ulpi-link";
508 status = "disabled";
483 }; 509 };
484 510
485 usb@c5008000 { 511 usb@c5008000 {
486 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 512 compatible = "nvidia,tegra20-ehci", "usb-ehci";
487 reg = <0xc5008000 0x4000>; 513 reg = <0xc5008000 0x4000>;
488 interrupts = <0 97 0x04>; 514 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
489 phy_type = "utmi"; 515 phy_type = "utmi";
490 clocks = <&tegra_car 59>; 516 clocks = <&tegra_car TEGRA20_CLK_USB3>;
491 nvidia,phy = <&phy3>; 517 nvidia,phy = <&phy3>;
492 status = "disabled"; 518 status = "disabled";
493 }; 519 };
494 520
495 phy3: usb-phy@c5008400 { 521 phy3: usb-phy@c5008000 {
496 compatible = "nvidia,tegra20-usb-phy"; 522 compatible = "nvidia,tegra20-usb-phy";
497 reg = <0xc5008400 0x3c00>; 523 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
498 phy_type = "utmi"; 524 phy_type = "utmi";
499 clocks = <&tegra_car 22>, <&tegra_car 127>; 525 clocks = <&tegra_car TEGRA20_CLK_USB3>,
500 clock-names = "phy", "pll_u"; 526 <&tegra_car TEGRA20_CLK_PLL_U>,
527 <&tegra_car TEGRA20_CLK_CLK_M>,
528 <&tegra_car TEGRA20_CLK_USBD>;
529 clock-names = "reg", "pll_u", "timer", "utmi-pads";
530 hssync_start_delay = <9>;
531 idle_wait_delay = <17>;
532 elastic_limit = <16>;
533 term_range_adj = <6>;
534 xcvr_setup = <9>;
535 xcvr_lsfslew = <2>;
536 xcvr_lsrslew = <2>;
537 status = "disabled";
501 }; 538 };
502 539
503 sdhci@c8000000 { 540 sdhci@c8000000 {
504 compatible = "nvidia,tegra20-sdhci"; 541 compatible = "nvidia,tegra20-sdhci";
505 reg = <0xc8000000 0x200>; 542 reg = <0xc8000000 0x200>;
506 interrupts = <0 14 0x04>; 543 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&tegra_car 14>; 544 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
508 status = "disabled"; 545 status = "disabled";
509 }; 546 };
510 547
511 sdhci@c8000200 { 548 sdhci@c8000200 {
512 compatible = "nvidia,tegra20-sdhci"; 549 compatible = "nvidia,tegra20-sdhci";
513 reg = <0xc8000200 0x200>; 550 reg = <0xc8000200 0x200>;
514 interrupts = <0 15 0x04>; 551 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&tegra_car 9>; 552 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
516 status = "disabled"; 553 status = "disabled";
517 }; 554 };
518 555
519 sdhci@c8000400 { 556 sdhci@c8000400 {
520 compatible = "nvidia,tegra20-sdhci"; 557 compatible = "nvidia,tegra20-sdhci";
521 reg = <0xc8000400 0x200>; 558 reg = <0xc8000400 0x200>;
522 interrupts = <0 19 0x04>; 559 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&tegra_car 69>; 560 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
524 status = "disabled"; 561 status = "disabled";
525 }; 562 };
526 563
527 sdhci@c8000600 { 564 sdhci@c8000600 {
528 compatible = "nvidia,tegra20-sdhci"; 565 compatible = "nvidia,tegra20-sdhci";
529 reg = <0xc8000600 0x200>; 566 reg = <0xc8000600 0x200>;
530 interrupts = <0 31 0x04>; 567 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&tegra_car 15>; 568 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
532 status = "disabled"; 569 status = "disabled";
533 }; 570 };
534 571
@@ -551,7 +588,7 @@
551 588
552 pmu { 589 pmu {
553 compatible = "arm,cortex-a9-pmu"; 590 compatible = "arm,cortex-a9-pmu";
554 interrupts = <0 56 0x04 591 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
555 0 57 0x04>; 592 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
556 }; 593 };
557}; 594};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b732f7c13a66..87c5f7b7c271 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1,13 +1,13 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra30.dtsi" 3#include "tegra30.dtsi"
4 4
5/ { 5/ {
6 model = "NVIDIA Tegra30 Beaver evaluation board"; 6 model = "NVIDIA Tegra30 Beaver evaluation board";
7 compatible = "nvidia,beaver", "nvidia,tegra30"; 7 compatible = "nvidia,beaver", "nvidia,tegra30";
8 8
9 memory { 9 memory {
10 reg = <0x80000000 0x80000000>; 10 reg = <0x80000000 0x7ff00000>;
11 }; 11 };
12 12
13 pinmux { 13 pinmux {
@@ -116,6 +116,15 @@
116 status = "okay"; 116 status = "okay";
117 clock-frequency = <100000>; 117 clock-frequency = <100000>;
118 118
119 rt5640: rt5640 {
120 compatible = "realtek,rt5640";
121 reg = <0x1c>;
122 interrupt-parent = <&gpio>;
123 interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
124 realtek,ldo1-en-gpios =
125 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
126 };
127
119 tps62361 { 128 tps62361 {
120 compatible = "ti,tps62361"; 129 compatible = "ti,tps62361";
121 reg = <0x60>; 130 reg = <0x60>;
@@ -133,7 +142,7 @@
133 compatible = "ti,tps65911"; 142 compatible = "ti,tps65911";
134 reg = <0x2d>; 143 reg = <0x2d>;
135 144
136 interrupts = <0 86 0x4>; 145 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
137 #interrupt-cells = <2>; 146 #interrupt-cells = <2>;
138 interrupt-controller; 147 interrupt-controller;
139 148
@@ -264,9 +273,9 @@
264 273
265 sdhci@78000000 { 274 sdhci@78000000 {
266 status = "okay"; 275 status = "okay";
267 cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 276 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
268 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 277 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
269 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 278 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
270 bus-width = <4>; 279 bus-width = <4>;
271 }; 280 };
272 281
@@ -312,7 +321,7 @@
312 regulator-boot-on; 321 regulator-boot-on;
313 regulator-always-on; 322 regulator-always-on;
314 enable-active-high; 323 enable-active-high;
315 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ 324 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
316 }; 325 };
317 326
318 ddr_reg: regulator@2 { 327 ddr_reg: regulator@2 {
@@ -324,7 +333,7 @@
324 regulator-always-on; 333 regulator-always-on;
325 regulator-boot-on; 334 regulator-boot-on;
326 enable-active-high; 335 enable-active-high;
327 gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */ 336 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
328 vin-supply = <&vdd_5v_in_reg>; 337 vin-supply = <&vdd_5v_in_reg>;
329 }; 338 };
330 339
@@ -337,7 +346,7 @@
337 regulator-always-on; 346 regulator-always-on;
338 regulator-boot-on; 347 regulator-boot-on;
339 enable-active-high; 348 enable-active-high;
340 gpio = <&gpio 30 0>; /* gpio PD6 */ 349 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
341 vin-supply = <&vdd_5v_in_reg>; 350 vin-supply = <&vdd_5v_in_reg>;
342 }; 351 };
343 352
@@ -348,7 +357,7 @@
348 regulator-min-microvolt = <5000000>; 357 regulator-min-microvolt = <5000000>;
349 regulator-max-microvolt = <5000000>; 358 regulator-max-microvolt = <5000000>;
350 enable-active-high; 359 enable-active-high;
351 gpio = <&gpio 68 0>; /* GPIO PI4 */ 360 gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
352 gpio-open-drain; 361 gpio-open-drain;
353 vin-supply = <&vdd_5v_in_reg>; 362 vin-supply = <&vdd_5v_in_reg>;
354 }; 363 };
@@ -360,7 +369,7 @@
360 regulator-min-microvolt = <5000000>; 369 regulator-min-microvolt = <5000000>;
361 regulator-max-microvolt = <5000000>; 370 regulator-max-microvolt = <5000000>;
362 enable-active-high; 371 enable-active-high;
363 gpio = <&gpio 63 0>; /* GPIO PH7 */ 372 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
364 gpio-open-drain; 373 gpio-open-drain;
365 vin-supply = <&vdd_5v_in_reg>; 374 vin-supply = <&vdd_5v_in_reg>;
366 }; 375 };
@@ -374,7 +383,7 @@
374 regulator-always-on; 383 regulator-always-on;
375 regulator-boot-on; 384 regulator-boot-on;
376 enable-active-high; 385 enable-active-high;
377 gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */ 386 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
378 vin-supply = <&vdd_5v_in_reg>; 387 vin-supply = <&vdd_5v_in_reg>;
379 }; 388 };
380 389
@@ -387,8 +396,41 @@
387 regulator-always-on; 396 regulator-always-on;
388 regulator-boot-on; 397 regulator-boot-on;
389 enable-active-high; 398 enable-active-high;
390 gpio = <&gpio 95 0>; /* gpio PL7 */ 399 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
391 vin-supply = <&sys_3v3_reg>; 400 vin-supply = <&sys_3v3_reg>;
392 }; 401 };
393 }; 402 };
403
404 gpio-leds {
405 compatible = "gpio-leds";
406
407 gpled1 {
408 label = "LED1"; /* CR5A1 (blue) */
409 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
410 };
411 gpled2 {
412 label = "LED2"; /* CR4A2 (green) */
413 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
414 };
415 };
416
417 sound {
418 compatible = "nvidia,tegra-audio-rt5640-beaver",
419 "nvidia,tegra-audio-rt5640";
420 nvidia,model = "NVIDIA Tegra Beaver";
421
422 nvidia,audio-routing =
423 "Headphones", "HPOR",
424 "Headphones", "HPOL";
425
426 nvidia,i2s-controller = <&tegra_i2s1>;
427 nvidia,audio-codec = <&rt5640>;
428
429 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
430
431 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
432 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
433 <&tegra_car TEGRA30_CLK_EXTERN1>;
434 clock-names = "pll_a", "pll_a_out0", "mclk";
435 };
394}; 436};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index e392bd2dab9b..1082c5ed90d1 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra30-cardhu.dtsi" 3#include "tegra30-cardhu.dtsi"
4 4
5/* This dts file support the cardhu A02 version of board */ 5/* This dts file support the cardhu A02 version of board */
6 6
@@ -22,7 +22,7 @@
22 regulator-always-on; 22 regulator-always-on;
23 regulator-boot-on; 23 regulator-boot-on;
24 enable-active-high; 24 enable-active-high;
25 gpio = <&pmic 6 0>; 25 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
26 }; 26 };
27 27
28 sys_3v3_reg: regulator@101 { 28 sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
34 regulator-always-on; 34 regulator-always-on;
35 regulator-boot-on; 35 regulator-boot-on;
36 enable-active-high; 36 enable-active-high;
37 gpio = <&pmic 7 0>; 37 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
38 }; 38 };
39 39
40 usb1_vbus_reg: regulator@102 { 40 usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
44 regulator-min-microvolt = <5000000>; 44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>; 45 regulator-max-microvolt = <5000000>;
46 enable-active-high; 46 enable-active-high;
47 gpio = <&gpio 68 0>; /* GPIO PI4 */ 47 gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
48 gpio-open-drain; 48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>; 49 vin-supply = <&vdd_5v0_reg>;
50 }; 50 };
@@ -56,7 +56,7 @@
56 regulator-min-microvolt = <5000000>; 56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>;
58 enable-active-high; 58 enable-active-high;
59 gpio = <&gpio 63 0>; /* GPIO PH7 */ 59 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
60 gpio-open-drain; 60 gpio-open-drain;
61 vin-supply = <&vdd_5v0_reg>; 61 vin-supply = <&vdd_5v0_reg>;
62 }; 62 };
@@ -68,7 +68,7 @@
68 regulator-min-microvolt = <5000000>; 68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>;
70 enable-active-high; 70 enable-active-high;
71 gpio = <&pmic 2 0>; 71 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
72 }; 72 };
73 73
74 vdd_bl_reg: regulator@105 { 74 vdd_bl_reg: regulator@105 {
@@ -80,13 +80,13 @@
80 regulator-always-on; 80 regulator-always-on;
81 regulator-boot-on; 81 regulator-boot-on;
82 enable-active-high; 82 enable-active-high;
83 gpio = <&gpio 83 0>; /* GPIO PK3 */ 83 gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
84 }; 84 };
85 }; 85 };
86 86
87 sdhci@78000400 { 87 sdhci@78000400 {
88 status = "okay"; 88 status = "okay";
89 power-gpios = <&gpio 28 0>; /* gpio PD4 */ 89 power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
90 bus-width = <4>; 90 bus-width = <4>;
91 keep-power-in-suspend; 91 keep-power-in-suspend;
92 }; 92 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index d0db6c7e774f..bf012bddaafb 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "tegra30-cardhu.dtsi" 3#include "tegra30-cardhu.dtsi"
4 4
5/* This dts file support the cardhu A04 and later versions of board */ 5/* This dts file support the cardhu A04 and later versions of board */
6 6
@@ -22,7 +22,7 @@
22 regulator-always-on; 22 regulator-always-on;
23 regulator-boot-on; 23 regulator-boot-on;
24 enable-active-high; 24 enable-active-high;
25 gpio = <&pmic 7 0>; 25 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
26 }; 26 };
27 27
28 sys_3v3_reg: regulator@101 { 28 sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
34 regulator-always-on; 34 regulator-always-on;
35 regulator-boot-on; 35 regulator-boot-on;
36 enable-active-high; 36 enable-active-high;
37 gpio = <&pmic 6 0>; 37 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
38 }; 38 };
39 39
40 usb1_vbus_reg: regulator@102 { 40 usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
44 regulator-min-microvolt = <5000000>; 44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>; 45 regulator-max-microvolt = <5000000>;
46 enable-active-high; 46 enable-active-high;
47 gpio = <&gpio 238 0>; /* GPIO PDD6 */ 47 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
48 gpio-open-drain; 48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>; 49 vin-supply = <&vdd_5v0_reg>;
50 }; 50 };
@@ -56,7 +56,7 @@
56 regulator-min-microvolt = <5000000>; 56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>;
58 enable-active-high; 58 enable-active-high;
59 gpio = <&gpio 236 0>; /* GPIO PDD4 */ 59 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
60 gpio-open-drain; 60 gpio-open-drain;
61 vin-supply = <&vdd_5v0_reg>; 61 vin-supply = <&vdd_5v0_reg>;
62 }; 62 };
@@ -68,7 +68,7 @@
68 regulator-min-microvolt = <5000000>; 68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>;
70 enable-active-high; 70 enable-active-high;
71 gpio = <&pmic 8 0>; 71 gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
72 }; 72 };
73 73
74 vdd_bl_reg: regulator@105 { 74 vdd_bl_reg: regulator@105 {
@@ -80,7 +80,7 @@
80 regulator-always-on; 80 regulator-always-on;
81 regulator-boot-on; 81 regulator-boot-on;
82 enable-active-high; 82 enable-active-high;
83 gpio = <&gpio 234 0>; /* GPIO PDD2 */ 83 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
84 }; 84 };
85 85
86 vdd_bl2_reg: regulator@106 { 86 vdd_bl2_reg: regulator@106 {
@@ -92,13 +92,13 @@
92 regulator-always-on; 92 regulator-always-on;
93 regulator-boot-on; 93 regulator-boot-on;
94 enable-active-high; 94 enable-active-high;
95 gpio = <&gpio 232 0>; /* GPIO PDD0 */ 95 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
96 }; 96 };
97 }; 97 };
98 98
99 sdhci@78000400 { 99 sdhci@78000400 {
100 status = "okay"; 100 status = "okay";
101 power-gpios = <&gpio 27 0>; /* gpio PD3 */ 101 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
102 bus-width = <4>; 102 bus-width = <4>;
103 keep-power-in-suspend; 103 keep-power-in-suspend;
104 }; 104 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 01b4c26fad96..f65b53d32416 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -1,4 +1,4 @@
1/include/ "tegra30.dtsi" 1#include "tegra30.dtsi"
2 2
3/** 3/**
4 * This file contains common DT entry for all fab version of Cardhu. 4 * This file contains common DT entry for all fab version of Cardhu.
@@ -146,7 +146,7 @@
146 compatible = "isil,isl29028"; 146 compatible = "isil,isl29028";
147 reg = <0x44>; 147 reg = <0x44>;
148 interrupt-parent = <&gpio>; 148 interrupt-parent = <&gpio>;
149 interrupts = <88 0x04>; /*gpio PL0 */ 149 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
150 }; 150 };
151 }; 151 };
152 152
@@ -163,7 +163,7 @@
163 compatible = "wlf,wm8903"; 163 compatible = "wlf,wm8903";
164 reg = <0x1a>; 164 reg = <0x1a>;
165 interrupt-parent = <&gpio>; 165 interrupt-parent = <&gpio>;
166 interrupts = <179 0x04>; /* gpio PW3 */ 166 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
167 167
168 gpio-controller; 168 gpio-controller;
169 #gpio-cells = <2>; 169 #gpio-cells = <2>;
@@ -190,7 +190,7 @@
190 compatible = "ti,tps65911"; 190 compatible = "ti,tps65911";
191 reg = <0x2d>; 191 reg = <0x2d>;
192 192
193 interrupts = <0 86 0x4>; 193 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
194 #interrupt-cells = <2>; 194 #interrupt-cells = <2>;
195 interrupt-controller; 195 interrupt-controller;
196 196
@@ -318,9 +318,9 @@
318 318
319 sdhci@78000000 { 319 sdhci@78000000 {
320 status = "okay"; 320 status = "okay";
321 cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 321 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
322 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 322 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
323 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 323 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
324 bus-width = <4>; 324 bus-width = <4>;
325 }; 325 };
326 326
@@ -364,7 +364,7 @@
364 regulator-min-microvolt = <1800000>; 364 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <1800000>; 365 regulator-max-microvolt = <1800000>;
366 enable-active-high; 366 enable-active-high;
367 gpio = <&gpio 220 0>; /* gpio PBB4 */ 367 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
368 vin-supply = <&vio_reg>; 368 vin-supply = <&vio_reg>;
369 }; 369 };
370 370
@@ -377,7 +377,7 @@
377 regulator-boot-on; 377 regulator-boot-on;
378 regulator-always-on; 378 regulator-always-on;
379 enable-active-high; 379 enable-active-high;
380 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ 380 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
381 }; 381 };
382 382
383 emmc_3v3_reg: regulator@3 { 383 emmc_3v3_reg: regulator@3 {
@@ -389,7 +389,7 @@
389 regulator-always-on; 389 regulator-always-on;
390 regulator-boot-on; 390 regulator-boot-on;
391 enable-active-high; 391 enable-active-high;
392 gpio = <&gpio 25 0>; /* gpio PD1 */ 392 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
393 vin-supply = <&sys_3v3_reg>; 393 vin-supply = <&sys_3v3_reg>;
394 }; 394 };
395 395
@@ -400,7 +400,7 @@
400 regulator-min-microvolt = <3300000>; 400 regulator-min-microvolt = <3300000>;
401 regulator-max-microvolt = <3300000>; 401 regulator-max-microvolt = <3300000>;
402 enable-active-high; 402 enable-active-high;
403 gpio = <&gpio 30 0>; /* gpio PD6 */ 403 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
404 }; 404 };
405 405
406 pex_hvdd_3v3_reg: regulator@5 { 406 pex_hvdd_3v3_reg: regulator@5 {
@@ -410,7 +410,7 @@
410 regulator-min-microvolt = <3300000>; 410 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>; 411 regulator-max-microvolt = <3300000>;
412 enable-active-high; 412 enable-active-high;
413 gpio = <&gpio 95 0>; /* gpio PL7 */ 413 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
414 vin-supply = <&sys_3v3_reg>; 414 vin-supply = <&sys_3v3_reg>;
415 }; 415 };
416 416
@@ -421,7 +421,7 @@
421 regulator-min-microvolt = <2800000>; 421 regulator-min-microvolt = <2800000>;
422 regulator-max-microvolt = <2800000>; 422 regulator-max-microvolt = <2800000>;
423 enable-active-high; 423 enable-active-high;
424 gpio = <&gpio 142 0>; /* gpio PR6 */ 424 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
425 vin-supply = <&sys_3v3_reg>; 425 vin-supply = <&sys_3v3_reg>;
426 }; 426 };
427 427
@@ -432,7 +432,7 @@
432 regulator-min-microvolt = <2800000>; 432 regulator-min-microvolt = <2800000>;
433 regulator-max-microvolt = <2800000>; 433 regulator-max-microvolt = <2800000>;
434 enable-active-high; 434 enable-active-high;
435 gpio = <&gpio 143 0>; /* gpio PR7 */ 435 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
436 vin-supply = <&sys_3v3_reg>; 436 vin-supply = <&sys_3v3_reg>;
437 }; 437 };
438 438
@@ -443,7 +443,7 @@
443 regulator-min-microvolt = <3300000>; 443 regulator-min-microvolt = <3300000>;
444 regulator-max-microvolt = <3300000>; 444 regulator-max-microvolt = <3300000>;
445 enable-active-high; 445 enable-active-high;
446 gpio = <&gpio 144 0>; /* gpio PS0 */ 446 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
447 vin-supply = <&sys_3v3_reg>; 447 vin-supply = <&sys_3v3_reg>;
448 }; 448 };
449 449
@@ -456,7 +456,7 @@
456 regulator-always-on; 456 regulator-always-on;
457 regulator-boot-on; 457 regulator-boot-on;
458 enable-active-high; 458 enable-active-high;
459 gpio = <&gpio 24 0>; /* gpio PD0 */ 459 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
460 vin-supply = <&sys_3v3_reg>; 460 vin-supply = <&sys_3v3_reg>;
461 }; 461 };
462 462
@@ -467,7 +467,7 @@
467 regulator-min-microvolt = <3300000>; 467 regulator-min-microvolt = <3300000>;
468 regulator-max-microvolt = <3300000>; 468 regulator-max-microvolt = <3300000>;
469 enable-active-high; 469 enable-active-high;
470 gpio = <&gpio 94 0>; /* gpio PL6 */ 470 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
471 vin-supply = <&sys_3v3_reg>; 471 vin-supply = <&sys_3v3_reg>;
472 }; 472 };
473 473
@@ -480,7 +480,7 @@
480 regulator-always-on; 480 regulator-always-on;
481 regulator-boot-on; 481 regulator-boot-on;
482 enable-active-high; 482 enable-active-high;
483 gpio = <&gpio 92 0>; /* gpio PL4 */ 483 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
484 vin-supply = <&sys_3v3_reg>; 484 vin-supply = <&sys_3v3_reg>;
485 }; 485 };
486 486
@@ -491,7 +491,7 @@
491 regulator-min-microvolt = <5000000>; 491 regulator-min-microvolt = <5000000>;
492 regulator-max-microvolt = <5000000>; 492 regulator-max-microvolt = <5000000>;
493 enable-active-high; 493 enable-active-high;
494 gpio = <&gpio 152 0>; /* GPIO PT0 */ 494 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
495 gpio-open-drain; 495 gpio-open-drain;
496 vin-supply = <&vdd_5v0_reg>; 496 vin-supply = <&vdd_5v0_reg>;
497 }; 497 };
@@ -515,10 +515,13 @@
515 nvidia,i2s-controller = <&tegra_i2s1>; 515 nvidia,i2s-controller = <&tegra_i2s1>;
516 nvidia,audio-codec = <&wm8903>; 516 nvidia,audio-codec = <&wm8903>;
517 517
518 nvidia,spkr-en-gpios = <&wm8903 2 0>; 518 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
519 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 519 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
520 GPIO_ACTIVE_HIGH>;
520 521
521 clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>; 522 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
523 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
524 <&tegra_car TEGRA30_CLK_EXTERN1>;
522 clock-names = "pll_a", "pll_a_out0", "mclk"; 525 clock-names = "pll_a", "pll_a_out0", "mclk";
523 }; 526 };
524}; 527};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15ded605142a..d8783f0fae63 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,8 @@
1/include/ "skeleton.dtsi" 1#include <dt-bindings/clock/tegra30-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h>
4
5#include "skeleton.dtsi"
2 6
3/ { 7/ {
4 compatible = "nvidia,tegra30"; 8 compatible = "nvidia,tegra30";
@@ -15,9 +19,9 @@
15 host1x { 19 host1x {
16 compatible = "nvidia,tegra30-host1x", "simple-bus"; 20 compatible = "nvidia,tegra30-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>; 21 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */ 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
19 0 67 0x04>; /* mpcore general */ 23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
20 clocks = <&tegra_car 28>; 24 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
21 25
22 #address-cells = <1>; 26 #address-cells = <1>;
23 #size-cells = <1>; 27 #size-cells = <1>;
@@ -27,36 +31,36 @@
27 mpe { 31 mpe {
28 compatible = "nvidia,tegra30-mpe"; 32 compatible = "nvidia,tegra30-mpe";
29 reg = <0x54040000 0x00040000>; 33 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>; 34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&tegra_car 60>; 35 clocks = <&tegra_car TEGRA30_CLK_MPE>;
32 }; 36 };
33 37
34 vi { 38 vi {
35 compatible = "nvidia,tegra30-vi"; 39 compatible = "nvidia,tegra30-vi";
36 reg = <0x54080000 0x00040000>; 40 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>; 41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&tegra_car 164>; 42 clocks = <&tegra_car TEGRA30_CLK_VI>;
39 }; 43 };
40 44
41 epp { 45 epp {
42 compatible = "nvidia,tegra30-epp"; 46 compatible = "nvidia,tegra30-epp";
43 reg = <0x540c0000 0x00040000>; 47 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>; 48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
45 clocks = <&tegra_car 19>; 49 clocks = <&tegra_car TEGRA30_CLK_EPP>;
46 }; 50 };
47 51
48 isp { 52 isp {
49 compatible = "nvidia,tegra30-isp"; 53 compatible = "nvidia,tegra30-isp";
50 reg = <0x54100000 0x00040000>; 54 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>; 55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
52 clocks = <&tegra_car 23>; 56 clocks = <&tegra_car TEGRA30_CLK_ISP>;
53 }; 57 };
54 58
55 gr2d { 59 gr2d {
56 compatible = "nvidia,tegra30-gr2d"; 60 compatible = "nvidia,tegra30-gr2d";
57 reg = <0x54140000 0x00040000>; 61 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>; 62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
59 clocks = <&tegra_car 21>; 63 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
60 }; 64 };
61 65
62 gr3d { 66 gr3d {
@@ -69,8 +73,9 @@
69 dc@54200000 { 73 dc@54200000 {
70 compatible = "nvidia,tegra30-dc"; 74 compatible = "nvidia,tegra30-dc";
71 reg = <0x54200000 0x00040000>; 75 reg = <0x54200000 0x00040000>;
72 interrupts = <0 73 0x04>; 76 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
73 clocks = <&tegra_car 27>, <&tegra_car 179>; 77 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
78 <&tegra_car TEGRA30_CLK_PLL_P>;
74 clock-names = "disp1", "parent"; 79 clock-names = "disp1", "parent";
75 80
76 rgb { 81 rgb {
@@ -81,8 +86,9 @@
81 dc@54240000 { 86 dc@54240000 {
82 compatible = "nvidia,tegra30-dc"; 87 compatible = "nvidia,tegra30-dc";
83 reg = <0x54240000 0x00040000>; 88 reg = <0x54240000 0x00040000>;
84 interrupts = <0 74 0x04>; 89 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&tegra_car 26>, <&tegra_car 179>; 90 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
91 <&tegra_car TEGRA30_CLK_PLL_P>;
86 clock-names = "disp2", "parent"; 92 clock-names = "disp2", "parent";
87 93
88 rgb { 94 rgb {
@@ -93,8 +99,9 @@
93 hdmi { 99 hdmi {
94 compatible = "nvidia,tegra30-hdmi"; 100 compatible = "nvidia,tegra30-hdmi";
95 reg = <0x54280000 0x00040000>; 101 reg = <0x54280000 0x00040000>;
96 interrupts = <0 75 0x04>; 102 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&tegra_car 51>, <&tegra_car 189>; 103 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
104 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
98 clock-names = "hdmi", "parent"; 105 clock-names = "hdmi", "parent";
99 status = "disabled"; 106 status = "disabled";
100 }; 107 };
@@ -102,15 +109,15 @@
102 tvo { 109 tvo {
103 compatible = "nvidia,tegra30-tvo"; 110 compatible = "nvidia,tegra30-tvo";
104 reg = <0x542c0000 0x00040000>; 111 reg = <0x542c0000 0x00040000>;
105 interrupts = <0 76 0x04>; 112 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&tegra_car 169>; 113 clocks = <&tegra_car TEGRA30_CLK_TVO>;
107 status = "disabled"; 114 status = "disabled";
108 }; 115 };
109 116
110 dsi { 117 dsi {
111 compatible = "nvidia,tegra30-dsi"; 118 compatible = "nvidia,tegra30-dsi";
112 reg = <0x54300000 0x00040000>; 119 reg = <0x54300000 0x00040000>;
113 clocks = <&tegra_car 48>; 120 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
114 status = "disabled"; 121 status = "disabled";
115 }; 122 };
116 }; 123 };
@@ -118,8 +125,9 @@
118 timer@50004600 { 125 timer@50004600 {
119 compatible = "arm,cortex-a9-twd-timer"; 126 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x50040600 0x20>; 127 reg = <0x50040600 0x20>;
121 interrupts = <1 13 0xf04>; 128 interrupts = <GIC_PPI 13
122 clocks = <&tegra_car 214>; 129 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
130 clocks = <&tegra_car TEGRA30_CLK_TWD>;
123 }; 131 };
124 132
125 intc: interrupt-controller { 133 intc: interrupt-controller {
@@ -142,13 +150,13 @@
142 timer@60005000 { 150 timer@60005000 {
143 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 151 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
144 reg = <0x60005000 0x400>; 152 reg = <0x60005000 0x400>;
145 interrupts = <0 0 0x04 153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
146 0 1 0x04 154 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
147 0 41 0x04 155 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
148 0 42 0x04 156 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
149 0 121 0x04 157 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
150 0 122 0x04>; 158 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&tegra_car 5>; 159 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
152 }; 160 };
153 161
154 tegra_car: clock { 162 tegra_car: clock {
@@ -160,39 +168,39 @@
160 apbdma: dma { 168 apbdma: dma {
161 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 169 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
162 reg = <0x6000a000 0x1400>; 170 reg = <0x6000a000 0x1400>;
163 interrupts = <0 104 0x04 171 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
164 0 105 0x04 172 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
165 0 106 0x04 173 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
166 0 107 0x04 174 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
167 0 108 0x04 175 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
168 0 109 0x04 176 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
169 0 110 0x04 177 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
170 0 111 0x04 178 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
171 0 112 0x04 179 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
172 0 113 0x04 180 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
173 0 114 0x04 181 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
174 0 115 0x04 182 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
175 0 116 0x04 183 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
176 0 117 0x04 184 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
177 0 118 0x04 185 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
178 0 119 0x04 186 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
179 0 128 0x04 187 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
180 0 129 0x04 188 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
181 0 130 0x04 189 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
182 0 131 0x04 190 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
183 0 132 0x04 191 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
184 0 133 0x04 192 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
185 0 134 0x04 193 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
186 0 135 0x04 194 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
187 0 136 0x04 195 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
188 0 137 0x04 196 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
189 0 138 0x04 197 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
190 0 139 0x04 198 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
191 0 140 0x04 199 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
192 0 141 0x04 200 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
193 0 142 0x04 201 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
194 0 143 0x04>; 202 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&tegra_car 34>; 203 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
196 }; 204 };
197 205
198 ahb: ahb { 206 ahb: ahb {
@@ -203,14 +211,14 @@
203 gpio: gpio { 211 gpio: gpio {
204 compatible = "nvidia,tegra30-gpio"; 212 compatible = "nvidia,tegra30-gpio";
205 reg = <0x6000d000 0x1000>; 213 reg = <0x6000d000 0x1000>;
206 interrupts = <0 32 0x04 214 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
207 0 33 0x04 215 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
208 0 34 0x04 216 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
209 0 35 0x04 217 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
210 0 55 0x04 218 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
211 0 87 0x04 219 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
212 0 89 0x04 220 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
213 0 125 0x04>; 221 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
214 #gpio-cells = <2>; 222 #gpio-cells = <2>;
215 gpio-controller; 223 gpio-controller;
216 #interrupt-cells = <2>; 224 #interrupt-cells = <2>;
@@ -235,9 +243,9 @@
235 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 243 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
236 reg = <0x70006000 0x40>; 244 reg = <0x70006000 0x40>;
237 reg-shift = <2>; 245 reg-shift = <2>;
238 interrupts = <0 36 0x04>; 246 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
239 nvidia,dma-request-selector = <&apbdma 8>; 247 nvidia,dma-request-selector = <&apbdma 8>;
240 clocks = <&tegra_car 6>; 248 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
241 status = "disabled"; 249 status = "disabled";
242 }; 250 };
243 251
@@ -245,9 +253,9 @@
245 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 253 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
246 reg = <0x70006040 0x40>; 254 reg = <0x70006040 0x40>;
247 reg-shift = <2>; 255 reg-shift = <2>;
248 interrupts = <0 37 0x04>; 256 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
249 nvidia,dma-request-selector = <&apbdma 9>; 257 nvidia,dma-request-selector = <&apbdma 9>;
250 clocks = <&tegra_car 160>; 258 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
251 status = "disabled"; 259 status = "disabled";
252 }; 260 };
253 261
@@ -255,9 +263,9 @@
255 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 263 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
256 reg = <0x70006200 0x100>; 264 reg = <0x70006200 0x100>;
257 reg-shift = <2>; 265 reg-shift = <2>;
258 interrupts = <0 46 0x04>; 266 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
259 nvidia,dma-request-selector = <&apbdma 10>; 267 nvidia,dma-request-selector = <&apbdma 10>;
260 clocks = <&tegra_car 55>; 268 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
261 status = "disabled"; 269 status = "disabled";
262 }; 270 };
263 271
@@ -265,9 +273,9 @@
265 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 273 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
266 reg = <0x70006300 0x100>; 274 reg = <0x70006300 0x100>;
267 reg-shift = <2>; 275 reg-shift = <2>;
268 interrupts = <0 90 0x04>; 276 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
269 nvidia,dma-request-selector = <&apbdma 19>; 277 nvidia,dma-request-selector = <&apbdma 19>;
270 clocks = <&tegra_car 65>; 278 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
271 status = "disabled"; 279 status = "disabled";
272 }; 280 };
273 281
@@ -275,9 +283,9 @@
275 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 283 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
276 reg = <0x70006400 0x100>; 284 reg = <0x70006400 0x100>;
277 reg-shift = <2>; 285 reg-shift = <2>;
278 interrupts = <0 91 0x04>; 286 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
279 nvidia,dma-request-selector = <&apbdma 20>; 287 nvidia,dma-request-selector = <&apbdma 20>;
280 clocks = <&tegra_car 66>; 288 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
281 status = "disabled"; 289 status = "disabled";
282 }; 290 };
283 291
@@ -285,24 +293,25 @@
285 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 293 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
286 reg = <0x7000a000 0x100>; 294 reg = <0x7000a000 0x100>;
287 #pwm-cells = <2>; 295 #pwm-cells = <2>;
288 clocks = <&tegra_car 17>; 296 clocks = <&tegra_car TEGRA30_CLK_PWM>;
289 status = "disabled"; 297 status = "disabled";
290 }; 298 };
291 299
292 rtc { 300 rtc {
293 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 301 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
294 reg = <0x7000e000 0x100>; 302 reg = <0x7000e000 0x100>;
295 interrupts = <0 2 0x04>; 303 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&tegra_car 4>; 304 clocks = <&tegra_car TEGRA30_CLK_RTC>;
297 }; 305 };
298 306
299 i2c@7000c000 { 307 i2c@7000c000 {
300 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 308 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
301 reg = <0x7000c000 0x100>; 309 reg = <0x7000c000 0x100>;
302 interrupts = <0 38 0x04>; 310 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
303 #address-cells = <1>; 311 #address-cells = <1>;
304 #size-cells = <0>; 312 #size-cells = <0>;
305 clocks = <&tegra_car 12>, <&tegra_car 182>; 313 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
314 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
306 clock-names = "div-clk", "fast-clk"; 315 clock-names = "div-clk", "fast-clk";
307 status = "disabled"; 316 status = "disabled";
308 }; 317 };
@@ -310,10 +319,11 @@
310 i2c@7000c400 { 319 i2c@7000c400 {
311 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 320 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
312 reg = <0x7000c400 0x100>; 321 reg = <0x7000c400 0x100>;
313 interrupts = <0 84 0x04>; 322 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>; 323 #address-cells = <1>;
315 #size-cells = <0>; 324 #size-cells = <0>;
316 clocks = <&tegra_car 54>, <&tegra_car 182>; 325 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
326 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
317 clock-names = "div-clk", "fast-clk"; 327 clock-names = "div-clk", "fast-clk";
318 status = "disabled"; 328 status = "disabled";
319 }; 329 };
@@ -321,10 +331,11 @@
321 i2c@7000c500 { 331 i2c@7000c500 {
322 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 332 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
323 reg = <0x7000c500 0x100>; 333 reg = <0x7000c500 0x100>;
324 interrupts = <0 92 0x04>; 334 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>; 335 #address-cells = <1>;
326 #size-cells = <0>; 336 #size-cells = <0>;
327 clocks = <&tegra_car 67>, <&tegra_car 182>; 337 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
338 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
328 clock-names = "div-clk", "fast-clk"; 339 clock-names = "div-clk", "fast-clk";
329 status = "disabled"; 340 status = "disabled";
330 }; 341 };
@@ -332,10 +343,11 @@
332 i2c@7000c700 { 343 i2c@7000c700 {
333 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 344 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
334 reg = <0x7000c700 0x100>; 345 reg = <0x7000c700 0x100>;
335 interrupts = <0 120 0x04>; 346 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>; 347 #address-cells = <1>;
337 #size-cells = <0>; 348 #size-cells = <0>;
338 clocks = <&tegra_car 103>, <&tegra_car 182>; 349 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
350 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
339 clock-names = "div-clk", "fast-clk"; 351 clock-names = "div-clk", "fast-clk";
340 status = "disabled"; 352 status = "disabled";
341 }; 353 };
@@ -343,10 +355,11 @@
343 i2c@7000d000 { 355 i2c@7000d000 {
344 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 356 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
345 reg = <0x7000d000 0x100>; 357 reg = <0x7000d000 0x100>;
346 interrupts = <0 53 0x04>; 358 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>; 359 #address-cells = <1>;
348 #size-cells = <0>; 360 #size-cells = <0>;
349 clocks = <&tegra_car 47>, <&tegra_car 182>; 361 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
362 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
350 clock-names = "div-clk", "fast-clk"; 363 clock-names = "div-clk", "fast-clk";
351 status = "disabled"; 364 status = "disabled";
352 }; 365 };
@@ -354,81 +367,81 @@
354 spi@7000d400 { 367 spi@7000d400 {
355 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 368 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
356 reg = <0x7000d400 0x200>; 369 reg = <0x7000d400 0x200>;
357 interrupts = <0 59 0x04>; 370 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
358 nvidia,dma-request-selector = <&apbdma 15>; 371 nvidia,dma-request-selector = <&apbdma 15>;
359 #address-cells = <1>; 372 #address-cells = <1>;
360 #size-cells = <0>; 373 #size-cells = <0>;
361 clocks = <&tegra_car 41>; 374 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
362 status = "disabled"; 375 status = "disabled";
363 }; 376 };
364 377
365 spi@7000d600 { 378 spi@7000d600 {
366 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 379 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
367 reg = <0x7000d600 0x200>; 380 reg = <0x7000d600 0x200>;
368 interrupts = <0 82 0x04>; 381 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
369 nvidia,dma-request-selector = <&apbdma 16>; 382 nvidia,dma-request-selector = <&apbdma 16>;
370 #address-cells = <1>; 383 #address-cells = <1>;
371 #size-cells = <0>; 384 #size-cells = <0>;
372 clocks = <&tegra_car 44>; 385 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
373 status = "disabled"; 386 status = "disabled";
374 }; 387 };
375 388
376 spi@7000d800 { 389 spi@7000d800 {
377 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 390 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
378 reg = <0x7000d800 0x200>; 391 reg = <0x7000d800 0x200>;
379 interrupts = <0 83 0x04>; 392 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
380 nvidia,dma-request-selector = <&apbdma 17>; 393 nvidia,dma-request-selector = <&apbdma 17>;
381 #address-cells = <1>; 394 #address-cells = <1>;
382 #size-cells = <0>; 395 #size-cells = <0>;
383 clocks = <&tegra_car 46>; 396 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
384 status = "disabled"; 397 status = "disabled";
385 }; 398 };
386 399
387 spi@7000da00 { 400 spi@7000da00 {
388 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 401 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
389 reg = <0x7000da00 0x200>; 402 reg = <0x7000da00 0x200>;
390 interrupts = <0 93 0x04>; 403 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
391 nvidia,dma-request-selector = <&apbdma 18>; 404 nvidia,dma-request-selector = <&apbdma 18>;
392 #address-cells = <1>; 405 #address-cells = <1>;
393 #size-cells = <0>; 406 #size-cells = <0>;
394 clocks = <&tegra_car 68>; 407 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
395 status = "disabled"; 408 status = "disabled";
396 }; 409 };
397 410
398 spi@7000dc00 { 411 spi@7000dc00 {
399 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 412 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
400 reg = <0x7000dc00 0x200>; 413 reg = <0x7000dc00 0x200>;
401 interrupts = <0 94 0x04>; 414 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
402 nvidia,dma-request-selector = <&apbdma 27>; 415 nvidia,dma-request-selector = <&apbdma 27>;
403 #address-cells = <1>; 416 #address-cells = <1>;
404 #size-cells = <0>; 417 #size-cells = <0>;
405 clocks = <&tegra_car 104>; 418 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
406 status = "disabled"; 419 status = "disabled";
407 }; 420 };
408 421
409 spi@7000de00 { 422 spi@7000de00 {
410 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 423 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
411 reg = <0x7000de00 0x200>; 424 reg = <0x7000de00 0x200>;
412 interrupts = <0 79 0x04>; 425 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
413 nvidia,dma-request-selector = <&apbdma 28>; 426 nvidia,dma-request-selector = <&apbdma 28>;
414 #address-cells = <1>; 427 #address-cells = <1>;
415 #size-cells = <0>; 428 #size-cells = <0>;
416 clocks = <&tegra_car 105>; 429 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
417 status = "disabled"; 430 status = "disabled";
418 }; 431 };
419 432
420 kbc { 433 kbc {
421 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 434 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
422 reg = <0x7000e200 0x100>; 435 reg = <0x7000e200 0x100>;
423 interrupts = <0 85 0x04>; 436 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&tegra_car 36>; 437 clocks = <&tegra_car TEGRA30_CLK_KBC>;
425 status = "disabled"; 438 status = "disabled";
426 }; 439 };
427 440
428 pmc { 441 pmc {
429 compatible = "nvidia,tegra30-pmc"; 442 compatible = "nvidia,tegra30-pmc";
430 reg = <0x7000e400 0x400>; 443 reg = <0x7000e400 0x400>;
431 clocks = <&tegra_car 218>, <&clk32k_in>; 444 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
432 clock-names = "pclk", "clk32k_in"; 445 clock-names = "pclk", "clk32k_in";
433 }; 446 };
434 447
@@ -438,7 +451,7 @@
438 0x7000f03c 0x1b4 451 0x7000f03c 0x1b4
439 0x7000f200 0x028 452 0x7000f200 0x028
440 0x7000f284 0x17c>; 453 0x7000f284 0x17c>;
441 interrupts = <0 77 0x04>; 454 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
442 }; 455 };
443 456
444 iommu { 457 iommu {
@@ -455,12 +468,19 @@
455 compatible = "nvidia,tegra30-ahub"; 468 compatible = "nvidia,tegra30-ahub";
456 reg = <0x70080000 0x200 469 reg = <0x70080000 0x200
457 0x70080200 0x100>; 470 0x70080200 0x100>;
458 interrupts = <0 103 0x04>; 471 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
459 nvidia,dma-request-selector = <&apbdma 1>; 472 nvidia,dma-request-selector = <&apbdma 1>;
460 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, 473 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
461 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, 474 <&tegra_car TEGRA30_CLK_APBIF>,
462 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, 475 <&tegra_car TEGRA30_CLK_I2S0>,
463 <&tegra_car 110>, <&tegra_car 162>; 476 <&tegra_car TEGRA30_CLK_I2S1>,
477 <&tegra_car TEGRA30_CLK_I2S2>,
478 <&tegra_car TEGRA30_CLK_I2S3>,
479 <&tegra_car TEGRA30_CLK_I2S4>,
480 <&tegra_car TEGRA30_CLK_DAM0>,
481 <&tegra_car TEGRA30_CLK_DAM1>,
482 <&tegra_car TEGRA30_CLK_DAM2>,
483 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
464 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 484 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
465 "i2s3", "i2s4", "dam0", "dam1", "dam2", 485 "i2s3", "i2s4", "dam0", "dam1", "dam2",
466 "spdif_in"; 486 "spdif_in";
@@ -472,7 +492,7 @@
472 compatible = "nvidia,tegra30-i2s"; 492 compatible = "nvidia,tegra30-i2s";
473 reg = <0x70080300 0x100>; 493 reg = <0x70080300 0x100>;
474 nvidia,ahub-cif-ids = <4 4>; 494 nvidia,ahub-cif-ids = <4 4>;
475 clocks = <&tegra_car 30>; 495 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
476 status = "disabled"; 496 status = "disabled";
477 }; 497 };
478 498
@@ -480,7 +500,7 @@
480 compatible = "nvidia,tegra30-i2s"; 500 compatible = "nvidia,tegra30-i2s";
481 reg = <0x70080400 0x100>; 501 reg = <0x70080400 0x100>;
482 nvidia,ahub-cif-ids = <5 5>; 502 nvidia,ahub-cif-ids = <5 5>;
483 clocks = <&tegra_car 11>; 503 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
484 status = "disabled"; 504 status = "disabled";
485 }; 505 };
486 506
@@ -488,7 +508,7 @@
488 compatible = "nvidia,tegra30-i2s"; 508 compatible = "nvidia,tegra30-i2s";
489 reg = <0x70080500 0x100>; 509 reg = <0x70080500 0x100>;
490 nvidia,ahub-cif-ids = <6 6>; 510 nvidia,ahub-cif-ids = <6 6>;
491 clocks = <&tegra_car 18>; 511 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
492 status = "disabled"; 512 status = "disabled";
493 }; 513 };
494 514
@@ -496,7 +516,7 @@
496 compatible = "nvidia,tegra30-i2s"; 516 compatible = "nvidia,tegra30-i2s";
497 reg = <0x70080600 0x100>; 517 reg = <0x70080600 0x100>;
498 nvidia,ahub-cif-ids = <7 7>; 518 nvidia,ahub-cif-ids = <7 7>;
499 clocks = <&tegra_car 101>; 519 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
500 status = "disabled"; 520 status = "disabled";
501 }; 521 };
502 522
@@ -504,7 +524,7 @@
504 compatible = "nvidia,tegra30-i2s"; 524 compatible = "nvidia,tegra30-i2s";
505 reg = <0x70080700 0x100>; 525 reg = <0x70080700 0x100>;
506 nvidia,ahub-cif-ids = <8 8>; 526 nvidia,ahub-cif-ids = <8 8>;
507 clocks = <&tegra_car 102>; 527 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
508 status = "disabled"; 528 status = "disabled";
509 }; 529 };
510 }; 530 };
@@ -512,32 +532,32 @@
512 sdhci@78000000 { 532 sdhci@78000000 {
513 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 533 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
514 reg = <0x78000000 0x200>; 534 reg = <0x78000000 0x200>;
515 interrupts = <0 14 0x04>; 535 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&tegra_car 14>; 536 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
517 status = "disabled"; 537 status = "disabled";
518 }; 538 };
519 539
520 sdhci@78000200 { 540 sdhci@78000200 {
521 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 541 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
522 reg = <0x78000200 0x200>; 542 reg = <0x78000200 0x200>;
523 interrupts = <0 15 0x04>; 543 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&tegra_car 9>; 544 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
525 status = "disabled"; 545 status = "disabled";
526 }; 546 };
527 547
528 sdhci@78000400 { 548 sdhci@78000400 {
529 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 549 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
530 reg = <0x78000400 0x200>; 550 reg = <0x78000400 0x200>;
531 interrupts = <0 19 0x04>; 551 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&tegra_car 69>; 552 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
533 status = "disabled"; 553 status = "disabled";
534 }; 554 };
535 555
536 sdhci@78000600 { 556 sdhci@78000600 {
537 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 557 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
538 reg = <0x78000600 0x200>; 558 reg = <0x78000600 0x200>;
539 interrupts = <0 31 0x04>; 559 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car 15>; 560 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
541 status = "disabled"; 561 status = "disabled";
542 }; 562 };
543 563
@@ -572,9 +592,9 @@
572 592
573 pmu { 593 pmu {
574 compatible = "arm,cortex-a9-pmu"; 594 compatible = "arm,cortex-a9-pmu";
575 interrupts = <0 144 0x04 595 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
576 0 145 0x04 596 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
577 0 146 0x04 597 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
578 0 147 0x04>; 598 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
579 }; 599 };
580}; 600};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 10:33:47 -0500