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authorMikko Perttunen <mperttunen@nvidia.com>2014-09-26 05:43:11 -0400
committerEduardo Valentin <edubezval@gmail.com>2014-11-20 09:43:17 -0500
commit26b76f80b32c824ea746cd17c70814f28935afc9 (patch)
tree4127e07e5ec6dfa6442c9f21a070ce2d04b8745c /arch/arm/boot
parent0199e9938f2c0e7f5476f5983f1763d28f049837 (diff)
ARM: tegra: Add soctherm and thermal zones to Tegra124 device tree
This adds the soctherm thermal sensing and management unit to the Tegra124 device tree along with the four thermal zones corresponding to the four thermal sensors provided by soctherm. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi47
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 478c555ebd96..41f8b274529a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -3,6 +3,7 @@
3#include <dt-bindings/pinctrl/pinctrl-tegra.h> 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/thermal/tegra124-soctherm.h>
6 7
7#include "skeleton.dtsi" 8#include "skeleton.dtsi"
8 9
@@ -640,6 +641,18 @@
640 status = "disabled"; 641 status = "disabled";
641 }; 642 };
642 643
644 soctherm: thermal-sensor@0,700e2000 {
645 compatible = "nvidia,tegra124-soctherm";
646 reg = <0x0 0x700e2000 0x0 0x1000>;
647 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
649 <&tegra_car TEGRA124_CLK_SOC_THERM>;
650 clock-names = "tsensor", "soctherm";
651 resets = <&tegra_car 78>;
652 reset-names = "soctherm";
653 #thermal-sensor-cells = <1>;
654 };
655
643 ahub@0,70300000 { 656 ahub@0,70300000 {
644 compatible = "nvidia,tegra124-ahub"; 657 compatible = "nvidia,tegra124-ahub";
645 reg = <0x0 0x70300000 0x0 0x200>, 658 reg = <0x0 0x70300000 0x0 0x200>,
@@ -881,6 +894,40 @@
881 }; 894 };
882 }; 895 };
883 896
897 thermal-zones {
898 cpu {
899 polling-delay-passive = <1000>;
900 polling-delay = <1000>;
901
902 thermal-sensors =
903 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
904 };
905
906 mem {
907 polling-delay-passive = <1000>;
908 polling-delay = <1000>;
909
910 thermal-sensors =
911 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
912 };
913
914 gpu {
915 polling-delay-passive = <1000>;
916 polling-delay = <1000>;
917
918 thermal-sensors =
919 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
920 };
921
922 pllx {
923 polling-delay-passive = <1000>;
924 polling-delay = <1000>;
925
926 thermal-sensors =
927 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
928 };
929 };
930
884 timer { 931 timer {
885 compatible = "arm,armv7-timer"; 932 compatible = "arm,armv7-timer";
886 interrupts = <GIC_PPI 13 933 interrupts = <GIC_PPI 13