Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  This time around, much of this is for at91, with the bulk of it being
  syscon and udc drivers.

  Also, there's:
   - coupled cpuidle support for Samsung Exynos4210
   - Renesas 73A0 common-clk work
   - of/platform changes to tear down DMA mappings on device destruction
   - a few updates to the TI Keystone knav code"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  cpuidle: exynos: add coupled cpuidle support for exynos4210
  ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary
  soc: ti: knav_qmss_queue: change knav_range_setup_acc_irq to static
  soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module
  pcmcia: at91_cf: depend on !ARCH_MULTIPLATFORM
  soc: ti: knav_qmss_queue: export API calls for use by user driver
  of/platform: teardown DMA mappings on device destruction
  usb: gadget: at91_udc: Allocate udc instance
  usb: gadget: at91_udc: Update DT binding documentation
  usb: gadget: at91_udc: Rework for multi-platform kernel support
  usb: gadget: at91_udc: Simplify probe and remove functions
  usb: gadget: at91_udc: Remove non-DT handling code
  usb: gadget: at91_udc: Document DT clocks and clock-names property
  usb: gadget: at91_udc: Drop uclk clock
  usb: gadget: at91_udc: Fix clock names
  mfd: syscon: Add Atmel SMC binding doc
  mfd: syscon: Add atmel-smc registers definition
  mfd: syscon: Add Atmel Matrix bus DT binding documentation
  mfd: syscon: Add atmel-matrix registers definition
  clk: shmobile: fix sparse NULL pointer warning
  ...

2 files changed, 362 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 863dc4c7d7f6..6d32c87632d4 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -182,6 +182,10 @@
         status = "okay";
 };
 
+&extal2_clk {
+        clock-frequency = <48000000>;
+};
+
 &i2c0 {
         status = "okay";
         as3711@40 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 37c8a761aeab..2dfd5b44255d 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -10,6 +10,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/sh73a0-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -71,6 +72,8 @@
 
                 renesas,channels-mask = <0x3f>;
 
+                clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
+                clock-names = "fck";
                 status = "disabled";
         };
 
@@ -160,6 +163,7 @@
                               0 168 IRQ_TYPE_LEVEL_HIGH
                               0 169 IRQ_TYPE_LEVEL_HIGH
                               0 170 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
                 status = "disabled";
         };
 
@@ -172,6 +176,7 @@
                               0 52 IRQ_TYPE_LEVEL_HIGH
                               0 53 IRQ_TYPE_LEVEL_HIGH
                               0 54 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
                 status = "disabled";
         };
 
@@ -184,6 +189,7 @@
                               0 172 IRQ_TYPE_LEVEL_HIGH
                               0 173 IRQ_TYPE_LEVEL_HIGH
                               0 174 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
                 status = "disabled";
         };
 
@@ -196,6 +202,7 @@
                               0 184 IRQ_TYPE_LEVEL_HIGH
                               0 185 IRQ_TYPE_LEVEL_HIGH
                               0 186 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
                 status = "disabled";
         };
 
@@ -208,6 +215,7 @@
                               0 188 IRQ_TYPE_LEVEL_HIGH
                               0 189 IRQ_TYPE_LEVEL_HIGH
                               0 190 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
                 status = "disabled";
         };
 
@@ -216,6 +224,7 @@
                 reg = <0xe6bd0000 0x100>;
                 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
                               0 141 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -226,6 +235,7 @@
                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
                               0 84 IRQ_TYPE_LEVEL_HIGH
                               0 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
@@ -236,6 +246,7 @@
                 reg = <0xee120000 0x100>;
                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
                               0 89 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
                 toshiba,mmc-wrprotect-disable;
                 cap-sd-highspeed;
                 status = "disabled";
@@ -246,6 +257,7 @@
                 reg = <0xee140000 0x100>;
                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
                               0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
                 toshiba,mmc-wrprotect-disable;
                 cap-sd-highspeed;
                 status = "disabled";
@@ -255,6 +267,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c40000 0x100>;
                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -262,6 +276,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c50000 0x100>;
                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -269,6 +285,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c60000 0x100>;
                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -276,6 +294,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c70000 0x100>;
                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -283,6 +303,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c80000 0x100>;
                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -290,6 +312,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6cb0000 0x100>;
                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -297,6 +321,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6cc0000 0x100>;
                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -304,6 +330,8 @@
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6cd0000 0x100>;
                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -311,6 +339,8 @@
                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
                 reg = <0xe6c30000 0x100>;
                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -338,4 +368,332 @@
                 interrupts = <0 146 0x4>;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* External root clocks */
+                extalr_clk: extalr_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "extalr";
+                };
+                extal1_clk: extal1_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <26000000>;
+                        clock-output-names = "extal1";
+                };
+                extal2_clk: extal2_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-output-names = "extal2";
+                };
+                extcki_clk: extcki_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-output-names = "extcki";
+                };
+                fsiack_clk: fsiack_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fsiack";
+                };
+                fsibck_clk: fsibck_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fsibck";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,sh73a0-cpg-clocks";
+                        reg = <0xe6150000 0x10000>;
+                        clocks = <&extal1_clk>, <&extal2_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll2",
+                                             "pll3", "dsi0phy", "dsi1phy",
+                                             "zg", "m3", "b", "m1", "m2",
+                                             "z", "zx", "hp";
+                };
+
+                /* Variable factor clocks (DIV6) */
+                vclk1_clk: vclk1_clk@e6150008 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150008 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk1";
+                };
+                vclk2_clk: vclk2_clk@e615000c {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615000c 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk2";
+                };
+                vclk3_clk: vclk3_clk@e615001c {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615001c 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk3";
+                };
+                zb_clk: zb_clk@e6150010 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150010 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "zb";
+                };
+                flctl_clk: flctl_clk@e6150014 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150014 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "flctlck";
+                };
+                sdhi0_clk: sdhi0_clk@e6150074 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150074 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sdhi0ck";
+                };
+                sdhi1_clk: sdhi1_clk@e6150078 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150078 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sdhi1ck";
+                };
+                sdhi2_clk: sdhi2_clk@e615007c {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615007c 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sdhi2ck";
+                };
+                fsia_clk: fsia_clk@e6150018 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150018 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fsia";
+                };
+                fsib_clk: fsib_clk@e6150090 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150090 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fsib";
+                };
+                sub_clk: sub_clk@e6150080 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150080 4>;
+                        clocks = <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sub";
+                };
+                spua_clk: spua_clk@e6150084 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150084 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "spua";
+                };
+                spuv_clk: spuv_clk@e6150094 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150094 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "spuv";
+                };
+                msu_clk: msu_clk@e6150088 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150088 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "msu";
+                };
+                hsi_clk: hsi_clk@e615008c {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615008c 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "hsi";
+                };
+                mfg1_clk: mfg1_clk@e6150098 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150098 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mfg1";
+                };
+                mfg2_clk: mfg2_clk@e615009c {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615009c 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mfg2";
+                };
+                dsit_clk: dsit_clk@e6150060 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150060 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "dsit";
+                };
+                dsi0p_clk: dsi0p_clk@e6150064 {
+                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150064 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "dsi0pck";
+                };
+
+                /* Fixed factor clocks */
+                main_div2_clk: main_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "main_div2";
+                };
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                pll1_div7_clk: pll1_div7_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <7>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div7";
+                };
+                pll1_div13_clk: pll1_div13_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <13>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div13";
+                };
+                twd_clk: twd_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks SH73A0_CLK_Z>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "twd";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150130 4>, <0xe6150030 4>;
+                        clocks = <&cpg_clocks SH73A0_CLK_HP>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_IIC2
+                        >;
+                        clock-output-names =
+                                "iic2";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150134 4>, <0xe6150038 4>;
+                        clocks = <&cpg_clocks SH73A0_CLK_B>,
+                                 <&cpg_clocks SH73A0_CLK_B>,
+                                 <&cpg_clocks SH73A0_CLK_B>,
+                                 <&cpg_clocks SH73A0_CLK_B>,
+                                 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
+                                 <&cpg_clocks SH73A0_CLK_HP>,
+                                 <&cpg_clocks SH73A0_CLK_ZG>,
+                                 <&cpg_clocks SH73A0_CLK_B>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
+                                SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
+                                SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
+                                SH73A0_CLK_IIC0 SH73A0_CLK_SGX
+                                SH73A0_CLK_LCDC0
+                        >;
+                        clock-output-names =
+                                "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
+                                "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150138 4>, <0xe6150040 4>;
+                        clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
+                                 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
+                                 <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
+                                 <&sub_clk>, <&sub_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
+                                SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
+                                SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
+                                SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
+                                SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
+                        >;
+                        clock-output-names =
+                                "scifa7", "sy_dmac", "mp_dmac", "scifa5",
+                                "scifb", "scifa0", "scifa1", "scifa2",
+                                "scifa3", "scifa4";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe615013c 4>, <0xe6150048 4>;
+                        clocks = <&sub_clk>, <&extalr_clk>,
+                                 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
+                                 <&cpg_clocks SH73A0_CLK_HP>,
+                                 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
+                                 <&sdhi0_clk>, <&sdhi1_clk>,
+                                 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
+                                 <&main_div2_clk>, <&main_div2_clk>,
+                                 <&main_div2_clk>, <&main_div2_clk>,
+                                 <&main_div2_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
+                                SH73A0_CLK_FSI SH73A0_CLK_IRDA
+                                SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
+                                SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
+                                SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
+                                SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
+                                SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
+                                SH73A0_CLK_TPU4
+                        >;
+                        clock-output-names =
+                                "scifa6", "cmt1", "fsi", "irda", "iic1",
+                                "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
+                                "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
+                };
+                mstp4_clks: mstp4_clks@e6150140 {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150140 4>, <0xe615004c 4>;
+                        clocks = <&cpg_clocks SH73A0_CLK_HP>,
+                                 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
+                                SH73A0_CLK_KEYSC
+                        >;
+                        clock-output-names =
+                                "iic3", "iic4", "keysc";
+                };
+        };
 };