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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:20:15 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:20:15 -0400
commite5ac320de1fe3ef5a5afa5f8a0cd19b0c5373a37 (patch)
tree022243a657a53921afe1cc86314cd6cb843cc28f /arch/arm/boot/dts
parent7d2b6ef19cf0f98cef17aa5185de3631a618710a (diff)
parent89522f0f8bd5056dec21bb7de073cbd5886e435c (diff)
Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform code changes from Olof Johansson: "The changes here belong to two main platforms: - Atmel At91 is flipping the bit and going multiplatform. This includes some cleanups and removal of code, and the final flip of config dependencies - Shmobile has several platforms that are going multiplatform, but this branch also contains a bunch of cleanups that they weren't able to keep separate in a good way. THere's also a removal of one of their SoCs and the corresponding boards (sh7372 and mackerel)" * tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (67 commits) ARM: at91/pm: move AT91_MEMCTRL_* to pm.h ARM: at91/pm: move the standby functions to pm.c ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected ARM: at91: add a Kconfig dependency on multi-platform ARM: at91: drop AT91_TIMER_HZ ARM: at91: remove hardware.h ARM: at91: remove SoC headers ARM: at91: remove useless mach/cpu.h ARM: at91: remove unused headers ARM: at91: switch at91_dt_defconfig to multiplatform ARM: at91: switch to multiplatform ARM: shmobile: r8a7778: enable multiplatform target ARM: shmobile: bockw: add sound to DT ARM: shmobile: r8a7778: add sound to DT ARM: shmobile: bockw: add devices hooked up to i2c0 to DT DT: i2c: add trivial binding for OKI ML86V7667 video decoder ARM: shmobile: r8a7778: common clock framework CPG driver ARM: shmobile: bockw dts: set extal clock frequency ARM: shmobile: bockw dts: Move Ethernet node to BSC ARM: shmobile: r8a73a4: Remove legacy code ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile10
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts156
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts37
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi557
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts174
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi293
-rw-r--r--arch/arm/boot/dts/sh7372-mackerel.dts26
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi35
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts398
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts376
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi163
11 files changed, 1557 insertions, 668 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0c219dfa0a7..a384cce5c31d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -475,25 +475,23 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
475 s5pv210-smdkv210.dtb \ 475 s5pv210-smdkv210.dtb \
476 s5pv210-torbreck.dtb 476 s5pv210-torbreck.dtb
477dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ 477dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
478 r8a73a4-ape6evm.dtb \
479 r8a73a4-ape6evm-reference.dtb \
480 r8a7740-armadillo800eva.dtb \ 478 r8a7740-armadillo800eva.dtb \
481 r8a7778-bockw.dtb \ 479 r8a7778-bockw.dtb \
482 r8a7778-bockw-reference.dtb \ 480 r8a7778-bockw-reference.dtb \
483 r8a7779-marzen.dtb \ 481 r8a7779-marzen.dtb \
484 sh7372-mackerel.dtb \ 482 sh73a0-kzm9g.dtb
485 sh73a0-kzm9g.dtb \
486 sh73a0-kzm9g-reference.dtb
487dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ 483dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
488 emev2-kzm9d.dtb \ 484 emev2-kzm9d.dtb \
489 r7s72100-genmai.dtb \ 485 r7s72100-genmai.dtb \
490 r8a73a4-ape6evm.dtb \ 486 r8a73a4-ape6evm.dtb \
491 r8a7740-armadillo800eva.dtb \ 487 r8a7740-armadillo800eva.dtb \
488 r8a7778-bockw.dtb \
492 r8a7779-marzen.dtb \ 489 r8a7779-marzen.dtb \
493 r8a7790-lager.dtb \ 490 r8a7790-lager.dtb \
494 r8a7791-henninger.dtb \ 491 r8a7791-henninger.dtb \
495 r8a7791-koelsch.dtb \ 492 r8a7791-koelsch.dtb \
496 r8a7794-alt.dtb 493 r8a7794-alt.dtb \
494 sh73a0-kzm9g.dtb
497dtb-$(CONFIG_ARCH_SOCFPGA) += \ 495dtb-$(CONFIG_ARCH_SOCFPGA) += \
498 socfpga_arria5_socdk.dtb \ 496 socfpga_arria5_socdk.dtb \
499 socfpga_arria10_socdk.dtb \ 497 socfpga_arria10_socdk.dtb \
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
deleted file mode 100644
index b3d8f844b57a..000000000000
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * Device Tree Source for the APE6EVM board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a73a4.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "APE6EVM";
17 compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
18
19 aliases {
20 serial0 = &scifa0;
21 };
22
23 chosen {
24 bootargs = "ignore_loglevel rw";
25 stdout-path = &scifa0;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0 0x40000000 0 0x40000000>;
31 };
32
33 memory@200000000 {
34 device_type = "memory";
35 reg = <2 0x00000000 0 0x40000000>;
36 };
37
38 vcc_mmc0: regulator@0 {
39 compatible = "regulator-fixed";
40 regulator-name = "MMC0 Vcc";
41 regulator-min-microvolt = <2800000>;
42 regulator-max-microvolt = <2800000>;
43 regulator-always-on;
44 };
45
46 vcc_sdhi0: regulator@1 {
47 compatible = "regulator-fixed";
48
49 regulator-name = "SDHI0 Vcc";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52
53 gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 };
56
57 /* Common 3.3V rail, used by several devices on APE6EVM */
58 ape6evm_fixed_3v3: regulator@2 {
59 compatible = "regulator-fixed";
60 regulator-name = "3V3";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-always-on;
64 };
65
66 lbsc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges = <0 0 0 0x20000000>;
71 };
72};
73
74&i2c5 {
75 status = "okay";
76 vdd_dvfs: max8973@1b {
77 compatible = "maxim,max8973";
78 reg = <0x1b>;
79
80 regulator-min-microvolt = <935000>;
81 regulator-max-microvolt = <1200000>;
82 regulator-boot-on;
83 regulator-always-on;
84 };
85};
86
87&cpu0 {
88 cpu0-supply = <&vdd_dvfs>;
89 operating-points = <
90 /* kHz uV */
91 1950000 1115000
92 1462500 995000
93 >;
94 voltage-tolerance = <1>; /* 1% */
95};
96
97&cmt1 {
98 status = "okay";
99};
100
101&pfc {
102 scifa0_pins: serial0 {
103 renesas,groups = "scifa0_data";
104 renesas,function = "scifa0";
105 };
106
107 mmc0_pins: mmc {
108 renesas,groups = "mmc0_data8", "mmc0_ctrl";
109 renesas,function = "mmc0";
110 };
111
112 sdhi0_pins: sd0 {
113 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
114 renesas,function = "sdhi0";
115 };
116
117 sdhi1_pins: sd1 {
118 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
119 renesas,function = "sdhi1";
120 };
121};
122
123&mmcif0 {
124 vmmc-supply = <&vcc_mmc0>;
125 bus-width = <8>;
126 non-removable;
127 pinctrl-names = "default";
128 pinctrl-0 = <&mmc0_pins>;
129 status = "okay";
130};
131
132&scifa0 {
133 pinctrl-0 = <&scifa0_pins>;
134 pinctrl-names = "default";
135
136 status = "okay";
137};
138
139&sdhi0 {
140 vmmc-supply = <&vcc_sdhi0>;
141 bus-width = <4>;
142 toshiba,mmc-wrprotect-disable;
143 pinctrl-names = "default";
144 pinctrl-0 = <&sdhi0_pins>;
145 status = "okay";
146};
147
148&sdhi1 {
149 vmmc-supply = <&ape6evm_fixed_3v3>;
150 bus-width = <4>;
151 broken-cd;
152 toshiba,mmc-wrprotect-disable;
153 pinctrl-names = "default";
154 pinctrl-0 = <&sdhi1_pins>;
155 status = "okay";
156};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index d1b6a07253ae..81a38ceee098 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -22,7 +22,7 @@
22 }; 22 };
23 23
24 chosen { 24 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 25 bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
26 stdout-path = &scifa0; 26 stdout-path = &scifa0;
27 }; 27 };
28 28
@@ -72,26 +72,6 @@
72 regulator-always-on; 72 regulator-always-on;
73 }; 73 };
74 74
75 lbsc {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges = <0 0 0 0x20000000>;
80
81 ethernet@8000000 {
82 compatible = "smsc,lan9220", "smsc,lan9115";
83 reg = <0x08000000 0x1000>;
84 interrupt-parent = <&irqc1>;
85 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
86 phy-mode = "mii";
87 reg-io-width = <4>;
88 smsc,irq-active-high;
89 smsc,irq-push-pull;
90 vdd33a-supply = <&ape6evm_fixed_3v3>;
91 vddvario-supply = <&ape6evm_fixed_1v8>;
92 };
93 };
94
95 leds { 75 leds {
96 compatible = "gpio-leds"; 76 compatible = "gpio-leds";
97 led1 { 77 led1 {
@@ -188,6 +168,21 @@
188 voltage-tolerance = <1>; /* 1% */ 168 voltage-tolerance = <1>; /* 1% */
189}; 169};
190 170
171&bsc {
172 ethernet@8000000 {
173 compatible = "smsc,lan9220", "smsc,lan9115";
174 reg = <0x08000000 0x1000>;
175 interrupt-parent = <&irqc1>;
176 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
177 phy-mode = "mii";
178 reg-io-width = <4>;
179 smsc,irq-active-high;
180 smsc,irq-push-pull;
181 vdd33a-supply = <&ape6evm_fixed_3v3>;
182 vddvario-supply = <&ape6evm_fixed_1v8>;
183 };
184};
185
191&cmt1 { 186&cmt1 {
192 status = "okay"; 187 status = "okay";
193}; 188};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 38136d9f6d95..0fd889f88109 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -9,6 +9,7 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12#include <dt-bindings/clock/r8a73a4-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
14 15
@@ -27,9 +28,15 @@
27 compatible = "arm,cortex-a15"; 28 compatible = "arm,cortex-a15";
28 reg = <0>; 29 reg = <0>;
29 clock-frequency = <1500000000>; 30 clock-frequency = <1500000000>;
31 power-domains = <&pd_a2sl>;
30 }; 32 };
31 }; 33 };
32 34
35 ptm {
36 compatible = "arm,coresight-etm3x";
37 power-domains = <&pd_d4>;
38 };
39
33 timer { 40 timer {
34 compatible = "arm,armv7-timer"; 41 compatible = "arm,armv7-timer";
35 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 42 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -41,11 +48,13 @@
41 dbsc1: memory-controller@e6790000 { 48 dbsc1: memory-controller@e6790000 {
42 compatible = "renesas,dbsc-r8a73a4"; 49 compatible = "renesas,dbsc-r8a73a4";
43 reg = <0 0xe6790000 0 0x10000>; 50 reg = <0 0xe6790000 0 0x10000>;
51 power-domains = <&pd_a3bc>;
44 }; 52 };
45 53
46 dbsc2: memory-controller@e67a0000 { 54 dbsc2: memory-controller@e67a0000 {
47 compatible = "renesas,dbsc-r8a73a4"; 55 compatible = "renesas,dbsc-r8a73a4";
48 reg = <0 0xe67a0000 0 0x10000>; 56 reg = <0 0xe67a0000 0 0x10000>;
57 power-domains = <&pd_a3bc>;
49 }; 58 };
50 59
51 dmac: dma-multiplexer { 60 dmac: dma-multiplexer {
@@ -87,38 +96,19 @@
87 "ch8", "ch9", "ch10", "ch11", 96 "ch8", "ch9", "ch10", "ch11",
88 "ch12", "ch13", "ch14", "ch15", 97 "ch12", "ch13", "ch14", "ch15",
89 "ch16", "ch17", "ch18", "ch19"; 98 "ch16", "ch17", "ch18", "ch19";
99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
100 power-domains = <&pd_a3sp>;
90 }; 101 };
91 }; 102 };
92 103
93 pfc: pfc@e6050000 {
94 compatible = "renesas,pfc-r8a73a4";
95 reg = <0 0xe6050000 0 0x9000>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupts-extended =
99 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
100 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
101 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
102 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
103 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
104 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
105 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
106 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
107 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
108 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
109 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
110 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
111 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
112 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
113 <&irqc1 24 0>, <&irqc1 25 0>;
114 };
115
116 i2c5: i2c@e60b0000 { 104 i2c5: i2c@e60b0000 {
117 #address-cells = <1>; 105 #address-cells = <1>;
118 #size-cells = <0>; 106 #size-cells = <0>;
119 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 107 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
120 reg = <0 0xe60b0000 0 0x428>; 108 reg = <0 0xe60b0000 0 0x428>;
121 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; 109 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
111 power-domains = <&pd_a3sp>;
122 112
123 status = "disabled"; 113 status = "disabled";
124 }; 114 };
@@ -127,6 +117,9 @@
127 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; 117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
128 reg = <0 0xe6130000 0 0x1004>; 118 reg = <0 0xe6130000 0 0x1004>;
129 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
121 clock-names = "fck";
122 power-domains = <&pd_c5>;
130 123
131 renesas,channels-mask = <0xff>; 124 renesas,channels-mask = <0xff>;
132 125
@@ -170,6 +163,7 @@
170 <0 29 IRQ_TYPE_LEVEL_HIGH>, 163 <0 29 IRQ_TYPE_LEVEL_HIGH>,
171 <0 30 IRQ_TYPE_LEVEL_HIGH>, 164 <0 30 IRQ_TYPE_LEVEL_HIGH>,
172 <0 31 IRQ_TYPE_LEVEL_HIGH>; 165 <0 31 IRQ_TYPE_LEVEL_HIGH>;
166 power-domains = <&pd_c4>;
173 }; 167 };
174 168
175 irqc1: interrupt-controller@e61c0200 { 169 irqc1: interrupt-controller@e61c0200 {
@@ -203,6 +197,31 @@
203 <0 55 IRQ_TYPE_LEVEL_HIGH>, 197 <0 55 IRQ_TYPE_LEVEL_HIGH>,
204 <0 56 IRQ_TYPE_LEVEL_HIGH>, 198 <0 56 IRQ_TYPE_LEVEL_HIGH>,
205 <0 57 IRQ_TYPE_LEVEL_HIGH>; 199 <0 57 IRQ_TYPE_LEVEL_HIGH>;
200 power-domains = <&pd_c4>;
201 };
202
203 pfc: pfc@e6050000 {
204 compatible = "renesas,pfc-r8a73a4";
205 reg = <0 0xe6050000 0 0x9000>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupts-extended =
209 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
210 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
211 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
212 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
213 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
214 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
215 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
216 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
217 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
218 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
219 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
220 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
221 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
222 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
223 <&irqc1 24 0>, <&irqc1 25 0>;
224 power-domains = <&pd_c5>;
206 }; 225 };
207 226
208 thermal@e61f0000 { 227 thermal@e61f0000 {
@@ -210,6 +229,8 @@
210 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 229 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
211 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 230 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
212 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 231 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
233 power-domains = <&pd_c5>;
213 }; 234 };
214 235
215 i2c0: i2c@e6500000 { 236 i2c0: i2c@e6500000 {
@@ -218,6 +239,8 @@
218 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 239 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
219 reg = <0 0xe6500000 0 0x428>; 240 reg = <0 0xe6500000 0 0x428>;
220 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
243 power-domains = <&pd_a3sp>;
221 status = "disabled"; 244 status = "disabled";
222 }; 245 };
223 246
@@ -227,6 +250,8 @@
227 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 250 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
228 reg = <0 0xe6510000 0 0x428>; 251 reg = <0 0xe6510000 0 0x428>;
229 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 252 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
254 power-domains = <&pd_a3sp>;
230 status = "disabled"; 255 status = "disabled";
231 }; 256 };
232 257
@@ -236,6 +261,8 @@
236 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 261 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
237 reg = <0 0xe6520000 0 0x428>; 262 reg = <0 0xe6520000 0 0x428>;
238 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
265 power-domains = <&pd_a3sp>;
239 status = "disabled"; 266 status = "disabled";
240 }; 267 };
241 268
@@ -245,6 +272,8 @@
245 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
246 reg = <0 0xe6530000 0 0x428>; 273 reg = <0 0xe6530000 0 0x428>;
247 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 274 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
276 power-domains = <&pd_a3sp>;
248 status = "disabled"; 277 status = "disabled";
249 }; 278 };
250 279
@@ -254,6 +283,8 @@
254 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 283 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
255 reg = <0 0xe6540000 0 0x428>; 284 reg = <0 0xe6540000 0 0x428>;
256 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 285 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
287 power-domains = <&pd_a3sp>;
257 status = "disabled"; 288 status = "disabled";
258 }; 289 };
259 290
@@ -263,6 +294,8 @@
263 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 294 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
264 reg = <0 0xe6550000 0 0x428>; 295 reg = <0 0xe6550000 0 0x428>;
265 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 296 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
298 power-domains = <&pd_a3sp>;
266 status = "disabled"; 299 status = "disabled";
267 }; 300 };
268 301
@@ -272,6 +305,8 @@
272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 305 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
273 reg = <0 0xe6560000 0 0x428>; 306 reg = <0 0xe6560000 0 0x428>;
274 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
309 power-domains = <&pd_a3sp>;
275 status = "disabled"; 310 status = "disabled";
276 }; 311 };
277 312
@@ -281,6 +316,8 @@
281 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 316 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
282 reg = <0 0xe6570000 0 0x428>; 317 reg = <0 0xe6570000 0 0x428>;
283 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 318 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
320 power-domains = <&pd_a3sp>;
284 status = "disabled"; 321 status = "disabled";
285 }; 322 };
286 323
@@ -288,6 +325,9 @@
288 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 325 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
289 reg = <0 0xe6c20000 0 0x100>; 326 reg = <0 0xe6c20000 0 0x100>;
290 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 327 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
329 clock-names = "sci_ick";
330 power-domains = <&pd_a3sp>;
291 status = "disabled"; 331 status = "disabled";
292 }; 332 };
293 333
@@ -295,6 +335,9 @@
295 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 335 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
296 reg = <0 0xe6c30000 0 0x100>; 336 reg = <0 0xe6c30000 0 0x100>;
297 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 337 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
339 clock-names = "sci_ick";
340 power-domains = <&pd_a3sp>;
298 status = "disabled"; 341 status = "disabled";
299 }; 342 };
300 343
@@ -302,6 +345,9 @@
302 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 345 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
303 reg = <0 0xe6c40000 0 0x100>; 346 reg = <0 0xe6c40000 0 0x100>;
304 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 347 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
349 clock-names = "sci_ick";
350 power-domains = <&pd_a3sp>;
305 status = "disabled"; 351 status = "disabled";
306 }; 352 };
307 353
@@ -309,6 +355,9 @@
309 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 355 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
310 reg = <0 0xe6c50000 0 0x100>; 356 reg = <0 0xe6c50000 0 0x100>;
311 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 357 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
359 clock-names = "sci_ick";
360 power-domains = <&pd_a3sp>;
312 status = "disabled"; 361 status = "disabled";
313 }; 362 };
314 363
@@ -316,6 +365,9 @@
316 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 365 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
317 reg = <0 0xe6ce0000 0 0x100>; 366 reg = <0 0xe6ce0000 0 0x100>;
318 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
369 clock-names = "sci_ick";
370 power-domains = <&pd_a3sp>;
319 status = "disabled"; 371 status = "disabled";
320 }; 372 };
321 373
@@ -323,6 +375,9 @@
323 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 375 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
324 reg = <0 0xe6cf0000 0 0x100>; 376 reg = <0 0xe6cf0000 0 0x100>;
325 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 377 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
379 clock-names = "sci_ick";
380 power-domains = <&pd_c4>;
326 status = "disabled"; 381 status = "disabled";
327 }; 382 };
328 383
@@ -330,6 +385,8 @@
330 compatible = "renesas,sdhi-r8a73a4"; 385 compatible = "renesas,sdhi-r8a73a4";
331 reg = <0 0xee100000 0 0x100>; 386 reg = <0 0xee100000 0 0x100>;
332 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
389 power-domains = <&pd_a3sp>;
333 cap-sd-highspeed; 390 cap-sd-highspeed;
334 status = "disabled"; 391 status = "disabled";
335 }; 392 };
@@ -338,6 +395,8 @@
338 compatible = "renesas,sdhi-r8a73a4"; 395 compatible = "renesas,sdhi-r8a73a4";
339 reg = <0 0xee120000 0 0x100>; 396 reg = <0 0xee120000 0 0x100>;
340 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
399 power-domains = <&pd_a3sp>;
341 cap-sd-highspeed; 400 cap-sd-highspeed;
342 status = "disabled"; 401 status = "disabled";
343 }; 402 };
@@ -346,6 +405,8 @@
346 compatible = "renesas,sdhi-r8a73a4"; 405 compatible = "renesas,sdhi-r8a73a4";
347 reg = <0 0xee140000 0 0x100>; 406 reg = <0 0xee140000 0 0x100>;
348 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 407 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
409 power-domains = <&pd_a3sp>;
349 cap-sd-highspeed; 410 cap-sd-highspeed;
350 status = "disabled"; 411 status = "disabled";
351 }; 412 };
@@ -354,6 +415,8 @@
354 compatible = "renesas,sh-mmcif"; 415 compatible = "renesas,sh-mmcif";
355 reg = <0 0xee200000 0 0x80>; 416 reg = <0 0xee200000 0 0x80>;
356 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 417 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
419 power-domains = <&pd_a3sp>;
357 reg-io-width = <4>; 420 reg-io-width = <4>;
358 status = "disabled"; 421 status = "disabled";
359 }; 422 };
@@ -362,6 +425,8 @@
362 compatible = "renesas,sh-mmcif"; 425 compatible = "renesas,sh-mmcif";
363 reg = <0 0xee220000 0 0x80>; 426 reg = <0 0xee220000 0 0x80>;
364 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
429 power-domains = <&pd_a3sp>;
365 reg-io-width = <4>; 430 reg-io-width = <4>;
366 status = "disabled"; 431 status = "disabled";
367 }; 432 };
@@ -377,4 +442,450 @@
377 <0 0xf1006000 0 0x2000>; 442 <0 0xf1006000 0 0x2000>;
378 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 443 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
379 }; 444 };
445
446 bsc: bus@fec10000 {
447 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
448 "simple-pm-bus";
449 #address-cells = <1>;
450 #size-cells = <1>;
451 ranges = <0 0 0 0x20000000>;
452 reg = <0 0xfec10000 0 0x400>;
453 clocks = <&zb_clk>;
454 power-domains = <&pd_c4>;
455 };
456
457 clocks {
458 #address-cells = <2>;
459 #size-cells = <2>;
460 ranges;
461
462 /* External root clocks */
463 extalr_clk: extalr_clk {
464 compatible = "fixed-clock";
465 #clock-cells = <0>;
466 clock-frequency = <32768>;
467 clock-output-names = "extalr";
468 };
469 extal1_clk: extal1_clk {
470 compatible = "fixed-clock";
471 #clock-cells = <0>;
472 clock-frequency = <25000000>;
473 clock-output-names = "extal1";
474 };
475 extal2_clk: extal2_clk {
476 compatible = "fixed-clock";
477 #clock-cells = <0>;
478 clock-frequency = <48000000>;
479 clock-output-names = "extal2";
480 };
481 fsiack_clk: fsiack_clk {
482 compatible = "fixed-clock";
483 #clock-cells = <0>;
484 /* This value must be overridden by the board. */
485 clock-frequency = <0>;
486 clock-output-names = "fsiack";
487 };
488 fsibck_clk: fsibck_clk {
489 compatible = "fixed-clock";
490 #clock-cells = <0>;
491 /* This value must be overridden by the board. */
492 clock-frequency = <0>;
493 clock-output-names = "fsibck";
494 };
495
496 /* Special CPG clocks */
497 cpg_clocks: cpg_clocks@e6150000 {
498 compatible = "renesas,r8a73a4-cpg-clocks";
499 reg = <0 0xe6150000 0 0x10000>;
500 clocks = <&extal1_clk>, <&extal2_clk>;
501 #clock-cells = <1>;
502 clock-output-names = "main", "pll0", "pll1", "pll2",
503 "pll2s", "pll2h", "z", "z2",
504 "i", "m3", "b", "m1", "m2",
505 "zx", "zs", "hp";
506 };
507
508 /* Variable factor clocks (DIV6) */
509 zb_clk: zb_clk@e6150010 {
510 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
511 reg = <0 0xe6150010 0 4>;
512 clocks = <&pll1_div2_clk>, <0>,
513 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
514 #clock-cells = <0>;
515 clock-output-names = "zb";
516 };
517 sdhi0_clk: sdhi0_clk@e6150074 {
518 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
519 reg = <0 0xe6150074 0 4>;
520 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
521 <0>, <&extal2_clk>;
522 #clock-cells = <0>;
523 clock-output-names = "sdhi0ck";
524 };
525 sdhi1_clk: sdhi1_clk@e6150078 {
526 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
527 reg = <0 0xe6150078 0 4>;
528 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
529 <0>, <&extal2_clk>;
530 #clock-cells = <0>;
531 clock-output-names = "sdhi1ck";
532 };
533 sdhi2_clk: sdhi2_clk@e615007c {
534 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
535 reg = <0 0xe615007c 0 4>;
536 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
537 <0>, <&extal2_clk>;
538 #clock-cells = <0>;
539 clock-output-names = "sdhi2ck";
540 };
541 mmc0_clk: mmc0_clk@e6150240 {
542 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
543 reg = <0 0xe6150240 0 4>;
544 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
545 <0>, <&extal2_clk>;
546 #clock-cells = <0>;
547 clock-output-names = "mmc0";
548 };
549 mmc1_clk: mmc1_clk@e6150244 {
550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
551 reg = <0 0xe6150244 0 4>;
552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 <0>, <&extal2_clk>;
554 #clock-cells = <0>;
555 clock-output-names = "mmc1";
556 };
557 vclk1_clk: vclk1_clk@e6150008 {
558 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
559 reg = <0 0xe6150008 0 4>;
560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
561 <0>, <&extal2_clk>, <&main_div2_clk>,
562 <&extalr_clk>, <0>, <0>;
563 #clock-cells = <0>;
564 clock-output-names = "vclk1";
565 };
566 vclk2_clk: vclk2_clk@e615000c {
567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
568 reg = <0 0xe615000c 0 4>;
569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
570 <0>, <&extal2_clk>, <&main_div2_clk>,
571 <&extalr_clk>, <0>, <0>;
572 #clock-cells = <0>;
573 clock-output-names = "vclk2";
574 };
575 vclk3_clk: vclk3_clk@e615001c {
576 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
577 reg = <0 0xe615001c 0 4>;
578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
579 <0>, <&extal2_clk>, <&main_div2_clk>,
580 <&extalr_clk>, <0>, <0>;
581 #clock-cells = <0>;
582 clock-output-names = "vclk3";
583 };
584 vclk4_clk: vclk4_clk@e6150014 {
585 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
586 reg = <0 0xe6150014 0 4>;
587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
588 <0>, <&extal2_clk>, <&main_div2_clk>,
589 <&extalr_clk>, <0>, <0>;
590 #clock-cells = <0>;
591 clock-output-names = "vclk4";
592 };
593 vclk5_clk: vclk5_clk@e6150034 {
594 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
595 reg = <0 0xe6150034 0 4>;
596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
597 <0>, <&extal2_clk>, <&main_div2_clk>,
598 <&extalr_clk>, <0>, <0>;
599 #clock-cells = <0>;
600 clock-output-names = "vclk5";
601 };
602 fsia_clk: fsia_clk@e6150018 {
603 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
604 reg = <0 0xe6150018 0 4>;
605 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
606 <&fsiack_clk>, <0>;
607 #clock-cells = <0>;
608 clock-output-names = "fsia";
609 };
610 fsib_clk: fsib_clk@e6150090 {
611 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
612 reg = <0 0xe6150090 0 4>;
613 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
614 <&fsibck_clk>, <0>;
615 #clock-cells = <0>;
616 clock-output-names = "fsib";
617 };
618 mp_clk: mp_clk@e6150080 {
619 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
620 reg = <0 0xe6150080 0 4>;
621 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
622 <&extal2_clk>, <&extal2_clk>;
623 #clock-cells = <0>;
624 clock-output-names = "mp";
625 };
626 m4_clk: m4_clk@e6150098 {
627 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
628 reg = <0 0xe6150098 0 4>;
629 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
630 #clock-cells = <0>;
631 clock-output-names = "m4";
632 };
633 hsi_clk: hsi_clk@e615026c {
634 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
635 reg = <0 0xe615026c 0 4>;
636 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
637 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
638 #clock-cells = <0>;
639 clock-output-names = "hsi";
640 };
641 spuv_clk: spuv_clk@e6150094 {
642 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
643 reg = <0 0xe6150094 0 4>;
644 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
645 <&extal2_clk>, <&extal2_clk>;
646 #clock-cells = <0>;
647 clock-output-names = "spuv";
648 };
649
650 /* Fixed factor clocks */
651 main_div2_clk: main_div2_clk {
652 compatible = "fixed-factor-clock";
653 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
654 #clock-cells = <0>;
655 clock-div = <2>;
656 clock-mult = <1>;
657 clock-output-names = "main_div2";
658 };
659 pll0_div2_clk: pll0_div2_clk {
660 compatible = "fixed-factor-clock";
661 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
662 #clock-cells = <0>;
663 clock-div = <2>;
664 clock-mult = <1>;
665 clock-output-names = "pll0_div2";
666 };
667 pll1_div2_clk: pll1_div2_clk {
668 compatible = "fixed-factor-clock";
669 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
670 #clock-cells = <0>;
671 clock-div = <2>;
672 clock-mult = <1>;
673 clock-output-names = "pll1_div2";
674 };
675 extal1_div2_clk: extal1_div2_clk {
676 compatible = "fixed-factor-clock";
677 clocks = <&extal1_clk>;
678 #clock-cells = <0>;
679 clock-div = <2>;
680 clock-mult = <1>;
681 clock-output-names = "extal1_div2";
682 };
683
684 /* Gate clocks */
685 mstp2_clks: mstp2_clks@e6150138 {
686 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
687 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
688 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
689 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
690 #clock-cells = <1>;
691 clock-indices = <
692 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
693 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
694 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
695 R8A73A4_CLK_DMAC
696 >;
697 clock-output-names =
698 "scifa0", "scifa1", "scifb0", "scifb1",
699 "scifb2", "scifb3", "dmac";
700 };
701 mstp3_clks: mstp3_clks@e615013c {
702 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
703 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
704 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
705 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
706 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
707 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
708 R8A73A4_CLK_HP>, <&cpg_clocks
709 R8A73A4_CLK_HP>, <&extalr_clk>;
710 #clock-cells = <1>;
711 clock-indices = <
712 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
713 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
714 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
715 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
716 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
717 R8A73A4_CLK_CMT1
718 >;
719 clock-output-names =
720 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
721 "mmcif0", "iic6", "iic7", "iic0", "iic1",
722 "cmt1";
723 };
724 mstp4_clks: mstp4_clks@e6150140 {
725 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
726 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
727 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
728 <&cpg_clocks R8A73A4_CLK_HP>;
729 #clock-cells = <1>;
730 clock-indices = <
731 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
732 R8A73A4_CLK_IIC3
733 >;
734 clock-output-names =
735 "iic5", "iic4", "iic3";
736 };
737 mstp5_clks: mstp5_clks@e6150144 {
738 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
739 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
740 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
741 #clock-cells = <1>;
742 clock-indices = <
743 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
744 >;
745 clock-output-names =
746 "thermal", "iic8";
747 };
748 };
749
750 sysc: system-controller@e6180000 {
751 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
752 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
753
754 pm-domains {
755 pd_c5: c5 {
756 #address-cells = <1>;
757 #size-cells = <0>;
758 #power-domain-cells = <0>;
759
760 pd_c4: c4@0 {
761 reg = <0>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 #power-domain-cells = <0>;
765
766 pd_a3sg: a3sg@16 {
767 reg = <16>;
768 #power-domain-cells = <0>;
769 };
770
771 pd_a3ex: a3ex@17 {
772 reg = <17>;
773 #power-domain-cells = <0>;
774 };
775
776 pd_a3sp: a3sp@18 {
777 reg = <18>;
778 #address-cells = <1>;
779 #size-cells = <0>;
780 #power-domain-cells = <0>;
781
782 pd_a2us: a2us@19 {
783 reg = <19>;
784 #power-domain-cells = <0>;
785 };
786 };
787
788 pd_a3sm: a3sm@20 {
789 reg = <20>;
790 #address-cells = <1>;
791 #size-cells = <0>;
792 #power-domain-cells = <0>;
793
794 pd_a2sl: a2sl@21 {
795 reg = <21>;
796 #power-domain-cells = <0>;
797 };
798 };
799
800 pd_a3km: a3km@22 {
801 reg = <22>;
802 #address-cells = <1>;
803 #size-cells = <0>;
804 #power-domain-cells = <0>;
805
806 pd_a2kl: a2kl@23 {
807 reg = <23>;
808 #power-domain-cells = <0>;
809 };
810 };
811 };
812
813 pd_c4ma: c4ma@1 {
814 reg = <1>;
815 #power-domain-cells = <0>;
816 };
817
818 pd_c4cl: c4cl@2 {
819 reg = <2>;
820 #power-domain-cells = <0>;
821 };
822
823 pd_d4: d4@3 {
824 reg = <3>;
825 #power-domain-cells = <0>;
826 };
827
828 pd_a4bc: a4bc@4 {
829 reg = <4>;
830 #address-cells = <1>;
831 #size-cells = <0>;
832 #power-domain-cells = <0>;
833
834 pd_a3bc: a3bc@5 {
835 reg = <5>;
836 #power-domain-cells = <0>;
837 };
838 };
839
840 pd_a4l: a4l@6 {
841 reg = <6>;
842 #power-domain-cells = <0>;
843 };
844
845 pd_a4lc: a4lc@7 {
846 reg = <7>;
847 #power-domain-cells = <0>;
848 };
849
850 pd_a4mp: a4mp@8 {
851 reg = <8>;
852 #address-cells = <1>;
853 #size-cells = <0>;
854 #power-domain-cells = <0>;
855
856 pd_a3mp: a3mp@9 {
857 reg = <9>;
858 #power-domain-cells = <0>;
859 };
860
861 pd_a3vc: a3vc@10 {
862 reg = <10>;
863 #power-domain-cells = <0>;
864 };
865 };
866
867 pd_a4sf: a4sf@11 {
868 reg = <11>;
869 #power-domain-cells = <0>;
870 };
871
872 pd_a3r: a3r@12 {
873 reg = <12>;
874 #address-cells = <1>;
875 #size-cells = <0>;
876 #power-domain-cells = <0>;
877
878 pd_a2rv: a2rv@13 {
879 reg = <13>;
880 #power-domain-cells = <0>;
881 };
882
883 pd_a2is: a2is@14 {
884 reg = <14>;
885 #power-domain-cells = <0>;
886 };
887 };
888 };
889 };
890 };
380}; 891};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 46a884d45175..787fa6f9f46d 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -16,17 +16,191 @@
16 16
17/dts-v1/; 17/dts-v1/;
18#include "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19#include <dt-bindings/interrupt-controller/irq.h>
20#include <dt-bindings/gpio/gpio.h>
19 21
20/ { 22/ {
21 model = "bockw"; 23 model = "bockw";
22 compatible = "renesas,bockw", "renesas,r8a7778"; 24 compatible = "renesas,bockw", "renesas,r8a7778";
23 25
26 aliases {
27 serial0 = &scif0;
28 };
29
24 chosen { 30 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; 31 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
32 stdout-path = &scif0;
26 }; 33 };
27 34
28 memory { 35 memory {
29 device_type = "memory"; 36 device_type = "memory";
30 reg = <0x60000000 0x10000000>; 37 reg = <0x60000000 0x10000000>;
31 }; 38 };
39
40 fixedregulator3v3: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "fixed-3.3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 sound {
50 compatible = "simple-audio-card";
51
52 simple-audio-card,format = "left_j";
53 simple-audio-card,bitclock-master = <&sndcodec>;
54 simple-audio-card,frame-master = <&sndcodec>;
55
56 sndcpu: simple-audio-card,cpu {
57 sound-dai = <&rcar_sound>;
58 };
59
60 sndcodec: simple-audio-card,codec {
61 sound-dai = <&ak4643>;
62 system-clock-frequency = <11289600>;
63 };
64 };
65};
66
67&bsc {
68 ethernet@18300000 {
69 compatible = "smsc,lan9220", "smsc,lan9115";
70 reg = <0x18300000 0x1000>;
71
72 phy-mode = "mii";
73 interrupt-parent = <&irqpin>;
74 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
75 reg-io-width = <4>;
76 vddvario-supply = <&fixedregulator3v3>;
77 vdd33a-supply = <&fixedregulator3v3>;
78 };
79};
80
81&extal_clk {
82 clock-frequency = <33333333>;
83};
84
85&i2c0 {
86 status = "okay";
87
88 ak4643: sound-codec@12 {
89 compatible = "asahi-kasei,ak4643";
90 #sound-dai-cells = <0>;
91 reg = <0x12>;
92 };
93
94 camera@41 {
95 compatible = "oki,ml86v7667";
96 reg = <0x41>;
97 };
98
99 camera@43 {
100 compatible = "oki,ml86v7667";
101 reg = <0x43>;
102 };
103
104 rx8581: rtc@51 {
105 compatible = "epson,rx8581";
106 reg = <0x51>;
107 };
108};
109
110&mmcif {
111 pinctrl-0 = <&mmc_pins>;
112 pinctrl-names = "default";
113
114 vmmc-supply = <&fixedregulator3v3>;
115 bus-width = <8>;
116 broken-cd;
117 status = "okay";
118};
119
120&irqpin {
121 status = "okay";
122};
123
124&tmu0 {
125 status = "okay";
126};
127
128&pfc {
129 scif0_pins: serial0 {
130 renesas,groups = "scif0_data_a", "scif0_ctrl";
131 renesas,function = "scif0";
132 };
133
134 mmc_pins: mmc {
135 renesas,groups = "mmc_data8", "mmc_ctrl";
136 renesas,function = "mmc";
137 };
138
139 sdhi0_pins: sd0 {
140 renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
141 "sdhi0_cd";
142 renesas,function = "sdhi0";
143 };
144
145 hspi0_pins: hspi0 {
146 renesas,groups = "hspi0_a";
147 renesas,function = "hspi0";
148 };
149
150 usb0_pins: usb0 {
151 renesas,groups = "usb0";
152 renesas,function = "usb0";
153 };
154
155 usb1_pins: usb1 {
156 renesas,groups = "usb1";
157 renesas,function = "usb1";
158 };
159
160 vin0_pins: vin0 {
161 renesas,groups = "vin0_data8", "vin0_clk";
162 renesas,function = "vin0";
163 };
164
165 vin1_pins: vin1 {
166 renesas,groups = "vin1_data8", "vin1_clk";
167 renesas,function = "vin1";
168 };
169};
170
171&sdhi0 {
172 pinctrl-0 = <&sdhi0_pins>;
173 pinctrl-names = "default";
174
175 vmmc-supply = <&fixedregulator3v3>;
176 bus-width = <4>;
177 status = "okay";
178 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
179};
180
181&hspi0 {
182 pinctrl-0 = <&hspi0_pins>;
183 pinctrl-names = "default";
184 status = "okay";
185
186 flash: flash@0 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "spansion,s25fl008k";
190 reg = <0>;
191 spi-max-frequency = <104000000>;
192 m25p,fast-read;
193
194 partition@0 {
195 label = "data(spi)";
196 reg = <0x00000000 0x00100000>;
197 };
198 };
199};
200
201&scif0 {
202 pinctrl-0 = <&scif0_pins>;
203 pinctrl-names = "default";
204
205 status = "okay";
32}; 206};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ef8533910029..868f97309533 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,7 @@
16 16
17/include/ "skeleton.dtsi" 17/include/ "skeleton.dtsi"
18 18
19#include <dt-bindings/clock/r8a7778-clock.h>
19#include <dt-bindings/interrupt-controller/irq.h> 20#include <dt-bindings/interrupt-controller/irq.h>
20 21
21/ { 22/ {
@@ -40,6 +41,24 @@
40 spi2 = &hspi2; 41 spi2 = &hspi2;
41 }; 42 };
42 43
44 bsc: bus@1c000000 {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0 0 0x1c000000>;
49 };
50
51 ether: ethernet@fde00000 {
52 compatible = "renesas,ether-r8a7778";
53 reg = <0xfde00000 0x400>;
54 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
56 phy-mode = "rmii";
57 #address-cells = <1>;
58 #size-cells = <0>;
59 status = "disabled";
60 };
61
43 gic: interrupt-controller@fe438000 { 62 gic: interrupt-controller@fe438000 {
44 compatible = "arm,cortex-a9-gic"; 63 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
@@ -132,6 +151,7 @@
132 compatible = "renesas,i2c-r8a7778"; 151 compatible = "renesas,i2c-r8a7778";
133 reg = <0xffc70000 0x1000>; 152 reg = <0xffc70000 0x1000>;
134 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
135 status = "disabled"; 155 status = "disabled";
136 }; 156 };
137 157
@@ -141,6 +161,7 @@
141 compatible = "renesas,i2c-r8a7778"; 161 compatible = "renesas,i2c-r8a7778";
142 reg = <0xffc71000 0x1000>; 162 reg = <0xffc71000 0x1000>;
143 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 163 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
144 status = "disabled"; 165 status = "disabled";
145 }; 166 };
146 167
@@ -150,6 +171,7 @@
150 compatible = "renesas,i2c-r8a7778"; 171 compatible = "renesas,i2c-r8a7778";
151 reg = <0xffc72000 0x1000>; 172 reg = <0xffc72000 0x1000>;
152 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
153 status = "disabled"; 175 status = "disabled";
154 }; 176 };
155 177
@@ -159,6 +181,7 @@
159 compatible = "renesas,i2c-r8a7778"; 181 compatible = "renesas,i2c-r8a7778";
160 reg = <0xffc73000 0x1000>; 182 reg = <0xffc73000 0x1000>;
161 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 183 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
162 status = "disabled"; 185 status = "disabled";
163 }; 186 };
164 187
@@ -168,6 +191,8 @@
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 191 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
169 <0 33 IRQ_TYPE_LEVEL_HIGH>, 192 <0 33 IRQ_TYPE_LEVEL_HIGH>,
170 <0 34 IRQ_TYPE_LEVEL_HIGH>; 193 <0 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
195 clock-names = "fck";
171 196
172 #renesas,channels = <3>; 197 #renesas,channels = <3>;
173 198
@@ -180,6 +205,8 @@
180 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 205 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
181 <0 37 IRQ_TYPE_LEVEL_HIGH>, 206 <0 37 IRQ_TYPE_LEVEL_HIGH>,
182 <0 38 IRQ_TYPE_LEVEL_HIGH>; 207 <0 38 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
209 clock-names = "fck";
183 210
184 #renesas,channels = <3>; 211 #renesas,channels = <3>;
185 212
@@ -192,16 +219,75 @@
192 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 219 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
193 <0 41 IRQ_TYPE_LEVEL_HIGH>, 220 <0 41 IRQ_TYPE_LEVEL_HIGH>,
194 <0 42 IRQ_TYPE_LEVEL_HIGH>; 221 <0 42 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
223 clock-names = "fck";
195 224
196 #renesas,channels = <3>; 225 #renesas,channels = <3>;
197 226
198 status = "disabled"; 227 status = "disabled";
199 }; 228 };
200 229
230 rcar_sound: sound@ffd90000 {
231 #sound-dai-cells = <1>;
232 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
233 reg = <0xffd90000 0x1000>, /* SRU */
234 <0xffd91000 0x1240>, /* SSI */
235 <0xfffe0000 0x24>; /* ADG */
236 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
237 <&mstp3_clks R8A7778_CLK_SSI7>,
238 <&mstp3_clks R8A7778_CLK_SSI6>,
239 <&mstp3_clks R8A7778_CLK_SSI5>,
240 <&mstp3_clks R8A7778_CLK_SSI4>,
241 <&mstp0_clks R8A7778_CLK_SSI3>,
242 <&mstp0_clks R8A7778_CLK_SSI2>,
243 <&mstp0_clks R8A7778_CLK_SSI1>,
244 <&mstp0_clks R8A7778_CLK_SSI0>,
245 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
246 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
247 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
248 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
249 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
250 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
251 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
252 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
253 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
254 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
255 <&cpg_clocks R8A7778_CLK_S1>;
256 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
257 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
258 "src.8", "src.7", "src.6", "src.5", "src.4",
259 "src.3", "src.2", "src.1", "src.0",
260 "clk_a", "clk_b", "clk_c", "clk_i";
261
262 status = "disabled";
263
264 rcar_sound,src {
265 src3: src@3 { };
266 src4: src@4 { };
267 src5: src@5 { };
268 src6: src@6 { };
269 src7: src@7 { };
270 src8: src@8 { };
271 src9: src@9 { };
272 };
273
274 rcar_sound,ssi {
275 ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
276 ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
277 ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
278 ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
279 ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
280 ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
281 ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
282 };
283 };
284
201 scif0: serial@ffe40000 { 285 scif0: serial@ffe40000 {
202 compatible = "renesas,scif-r8a7778", "renesas,scif"; 286 compatible = "renesas,scif-r8a7778", "renesas,scif";
203 reg = <0xffe40000 0x100>; 287 reg = <0xffe40000 0x100>;
204 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 288 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
290 clock-names = "sci_ick";
205 status = "disabled"; 291 status = "disabled";
206 }; 292 };
207 293
@@ -209,6 +295,8 @@
209 compatible = "renesas,scif-r8a7778", "renesas,scif"; 295 compatible = "renesas,scif-r8a7778", "renesas,scif";
210 reg = <0xffe41000 0x100>; 296 reg = <0xffe41000 0x100>;
211 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
299 clock-names = "sci_ick";
212 status = "disabled"; 300 status = "disabled";
213 }; 301 };
214 302
@@ -216,6 +304,8 @@
216 compatible = "renesas,scif-r8a7778", "renesas,scif"; 304 compatible = "renesas,scif-r8a7778", "renesas,scif";
217 reg = <0xffe42000 0x100>; 305 reg = <0xffe42000 0x100>;
218 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 306 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
308 clock-names = "sci_ick";
219 status = "disabled"; 309 status = "disabled";
220 }; 310 };
221 311
@@ -223,6 +313,8 @@
223 compatible = "renesas,scif-r8a7778", "renesas,scif"; 313 compatible = "renesas,scif-r8a7778", "renesas,scif";
224 reg = <0xffe43000 0x100>; 314 reg = <0xffe43000 0x100>;
225 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
317 clock-names = "sci_ick";
226 status = "disabled"; 318 status = "disabled";
227 }; 319 };
228 320
@@ -230,6 +322,8 @@
230 compatible = "renesas,scif-r8a7778", "renesas,scif"; 322 compatible = "renesas,scif-r8a7778", "renesas,scif";
231 reg = <0xffe44000 0x100>; 323 reg = <0xffe44000 0x100>;
232 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 324 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
326 clock-names = "sci_ick";
233 status = "disabled"; 327 status = "disabled";
234 }; 328 };
235 329
@@ -237,6 +331,8 @@
237 compatible = "renesas,scif-r8a7778", "renesas,scif"; 331 compatible = "renesas,scif-r8a7778", "renesas,scif";
238 reg = <0xffe45000 0x100>; 332 reg = <0xffe45000 0x100>;
239 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
335 clock-names = "sci_ick";
240 status = "disabled"; 336 status = "disabled";
241 }; 337 };
242 338
@@ -244,6 +340,7 @@
244 compatible = "renesas,sh-mmcif"; 340 compatible = "renesas,sh-mmcif";
245 reg = <0xffe4e000 0x100>; 341 reg = <0xffe4e000 0x100>;
246 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
247 status = "disabled"; 344 status = "disabled";
248 }; 345 };
249 346
@@ -251,6 +348,7 @@
251 compatible = "renesas,sdhi-r8a7778"; 348 compatible = "renesas,sdhi-r8a7778";
252 reg = <0xffe4c000 0x100>; 349 reg = <0xffe4c000 0x100>;
253 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
254 status = "disabled"; 352 status = "disabled";
255 }; 353 };
256 354
@@ -258,6 +356,7 @@
258 compatible = "renesas,sdhi-r8a7778"; 356 compatible = "renesas,sdhi-r8a7778";
259 reg = <0xffe4d000 0x100>; 357 reg = <0xffe4d000 0x100>;
260 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
261 status = "disabled"; 360 status = "disabled";
262 }; 361 };
263 362
@@ -265,6 +364,7 @@
265 compatible = "renesas,sdhi-r8a7778"; 364 compatible = "renesas,sdhi-r8a7778";
266 reg = <0xffe4f000 0x100>; 365 reg = <0xffe4f000 0x100>;
267 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 366 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
268 status = "disabled"; 368 status = "disabled";
269 }; 369 };
270 370
@@ -272,6 +372,7 @@
272 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 372 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
273 reg = <0xfffc7000 0x18>; 373 reg = <0xfffc7000 0x18>;
274 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 374 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
275 #address-cells = <1>; 376 #address-cells = <1>;
276 #size-cells = <0>; 377 #size-cells = <0>;
277 status = "disabled"; 378 status = "disabled";
@@ -281,6 +382,7 @@
281 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 382 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
282 reg = <0xfffc8000 0x18>; 383 reg = <0xfffc8000 0x18>;
283 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 384 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
284 #address-cells = <1>; 386 #address-cells = <1>;
285 #size-cells = <0>; 387 #size-cells = <0>;
286 status = "disabled"; 388 status = "disabled";
@@ -290,8 +392,199 @@
290 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 392 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
291 reg = <0xfffc6000 0x18>; 393 reg = <0xfffc6000 0x18>;
292 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 394 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
293 #address-cells = <1>; 396 #address-cells = <1>;
294 #size-cells = <0>; 397 #size-cells = <0>;
295 status = "disabled"; 398 status = "disabled";
296 }; 399 };
400
401 clocks {
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405
406 /* External input clock */
407 extal_clk: extal_clk {
408 compatible = "fixed-clock";
409 #clock-cells = <0>;
410 clock-frequency = <0>;
411 clock-output-names = "extal";
412 };
413
414 /* Special CPG clocks */
415 cpg_clocks: cpg_clocks@ffc80000 {
416 compatible = "renesas,r8a7778-cpg-clocks";
417 reg = <0xffc80000 0x80>;
418 #clock-cells = <1>;
419 clocks = <&extal_clk>;
420 clock-output-names = "plla", "pllb", "b",
421 "out", "p", "s", "s1";
422 };
423
424 /* Audio clocks; frequencies are set by boards if applicable. */
425 audio_clk_a: audio_clk_a {
426 compatible = "fixed-clock";
427 #clock-cells = <0>;
428 clock-output-names = "audio_clk_a";
429 };
430 audio_clk_b: audio_clk_b {
431 compatible = "fixed-clock";
432 #clock-cells = <0>;
433 clock-output-names = "audio_clk_b";
434 };
435 audio_clk_c: audio_clk_c {
436 compatible = "fixed-clock";
437 #clock-cells = <0>;
438 clock-output-names = "audio_clk_c";
439 };
440
441 /* Fixed ratio clocks */
442 g_clk: g_clk {
443 compatible = "fixed-factor-clock";
444 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
445 #clock-cells = <0>;
446 clock-div = <12>;
447 clock-mult = <1>;
448 clock-output-names = "g";
449 };
450 i_clk: i_clk {
451 compatible = "fixed-factor-clock";
452 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
453 #clock-cells = <0>;
454 clock-div = <1>;
455 clock-mult = <1>;
456 clock-output-names = "i";
457 };
458 s3_clk: s3_clk {
459 compatible = "fixed-factor-clock";
460 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
461 #clock-cells = <0>;
462 clock-div = <4>;
463 clock-mult = <1>;
464 clock-output-names = "s3";
465 };
466 s4_clk: s4_clk {
467 compatible = "fixed-factor-clock";
468 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
469 #clock-cells = <0>;
470 clock-div = <8>;
471 clock-mult = <1>;
472 clock-output-names = "s4";
473 };
474 z_clk: z_clk {
475 compatible = "fixed-factor-clock";
476 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
477 #clock-cells = <0>;
478 clock-div = <1>;
479 clock-mult = <1>;
480 clock-output-names = "z";
481 };
482
483 /* Gate clocks */
484 mstp0_clks: mstp0_clks@ffc80030 {
485 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
486 reg = <0xffc80030 4>;
487 clocks = <&cpg_clocks R8A7778_CLK_P>,
488 <&cpg_clocks R8A7778_CLK_P>,
489 <&cpg_clocks R8A7778_CLK_P>,
490 <&cpg_clocks R8A7778_CLK_P>,
491 <&cpg_clocks R8A7778_CLK_P>,
492 <&cpg_clocks R8A7778_CLK_P>,
493 <&cpg_clocks R8A7778_CLK_P>,
494 <&cpg_clocks R8A7778_CLK_P>,
495 <&cpg_clocks R8A7778_CLK_P>,
496 <&cpg_clocks R8A7778_CLK_P>,
497 <&cpg_clocks R8A7778_CLK_P>,
498 <&cpg_clocks R8A7778_CLK_P>,
499 <&cpg_clocks R8A7778_CLK_P>,
500 <&cpg_clocks R8A7778_CLK_P>,
501 <&cpg_clocks R8A7778_CLK_P>,
502 <&cpg_clocks R8A7778_CLK_P>,
503 <&cpg_clocks R8A7778_CLK_P>,
504 <&cpg_clocks R8A7778_CLK_P>,
505 <&cpg_clocks R8A7778_CLK_S>;
506 #clock-cells = <1>;
507 clock-indices = <
508 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
509 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
510 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
511 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
512 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
513 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
514 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
515 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
516 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
517 R8A7778_CLK_HSPI
518 >;
519 clock-output-names =
520 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
521 "scif1", "scif2", "scif3", "scif4", "scif5",
522 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
523 "ssi2", "ssi3", "sru", "hspi";
524 };
525 mstp1_clks: mstp1_clks@ffc80034 {
526 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
527 reg = <0xffc80034 4>, <0xffc80044 4>;
528 clocks = <&cpg_clocks R8A7778_CLK_P>,
529 <&cpg_clocks R8A7778_CLK_S>,
530 <&cpg_clocks R8A7778_CLK_S>,
531 <&cpg_clocks R8A7778_CLK_P>;
532 #clock-cells = <1>;
533 clock-indices = <
534 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
535 R8A7778_CLK_VIN1 R8A7778_CLK_USB
536 >;
537 clock-output-names =
538 "ether", "vin0", "vin1", "usb";
539 };
540 mstp3_clks: mstp3_clks@ffc8003c {
541 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
542 reg = <0xffc8003c 4>;
543 clocks = <&s4_clk>,
544 <&cpg_clocks R8A7778_CLK_P>,
545 <&cpg_clocks R8A7778_CLK_P>,
546 <&cpg_clocks R8A7778_CLK_P>,
547 <&cpg_clocks R8A7778_CLK_P>,
548 <&cpg_clocks R8A7778_CLK_P>,
549 <&cpg_clocks R8A7778_CLK_P>,
550 <&cpg_clocks R8A7778_CLK_P>,
551 <&cpg_clocks R8A7778_CLK_P>;
552 #clock-cells = <1>;
553 clock-indices = <
554 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
555 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
556 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
557 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
558 R8A7778_CLK_SSI8
559 >;
560 clock-output-names =
561 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
562 "ssi5", "ssi6", "ssi7", "ssi8";
563 };
564 mstp5_clks: mstp5_clks@ffc80054 {
565 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
566 reg = <0xffc80054 4>;
567 clocks = <&cpg_clocks R8A7778_CLK_P>,
568 <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_P>,
570 <&cpg_clocks R8A7778_CLK_P>,
571 <&cpg_clocks R8A7778_CLK_P>,
572 <&cpg_clocks R8A7778_CLK_P>,
573 <&cpg_clocks R8A7778_CLK_P>,
574 <&cpg_clocks R8A7778_CLK_P>,
575 <&cpg_clocks R8A7778_CLK_P>;
576 #clock-cells = <1>;
577 clock-indices = <
578 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
579 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
580 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
581 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
582 R8A7778_CLK_SRU_SRC8
583 >;
584 clock-output-names =
585 "sru-src0", "sru-src1", "sru-src2",
586 "sru-src3", "sru-src4", "sru-src5",
587 "sru-src6", "sru-src7", "sru-src8";
588 };
589 };
297}; 590};
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
deleted file mode 100644
index a759a276c9a9..000000000000
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Device Tree Source for the mackerel board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "sh7372.dtsi"
13
14/ {
15 model = "Mackerel (AP4 EVM 2nd)";
16 compatible = "renesas,mackerel";
17
18 chosen {
19 bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x40000000 0x10000000>;
25 };
26};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
deleted file mode 100644
index f863a10cb1b2..000000000000
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Device Tree Source for the sh7372 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7372";
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 device_type = "cpu";
23 reg = <0x0>;
24 clock-frequency = <800000000>;
25 };
26 };
27
28 pfc: pfc@e6050000 {
29 compatible = "renesas,pfc-sh7372";
30 reg = <0xe6050000 0x8000>,
31 <0xe605801c 0x1c>;
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
deleted file mode 100644
index bf365f7fef47..000000000000
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * Device Tree Source for the KZM-A9-GT board
3 *
4 * Copyright (C) 2012 Horms Solutions Ltd.
5 *
6 * Based on sh73a0-kzm9g.dts
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14/dts-v1/;
15#include "sh73a0.dtsi"
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21 model = "KZM-A9-GT";
22 compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
23
24 aliases {
25 serial4 = &scifa4;
26 };
27
28 cpus {
29 cpu@0 {
30 cpu0-supply = <&vdd_dvfs>;
31 operating-points = <
32 /* kHz uV */
33 1196000 1315000
34 598000 1175000
35 398667 1065000
36 >;
37 voltage-tolerance = <1>; /* 1% */
38 };
39 };
40
41 chosen {
42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
43 stdout-path = &scifa4;
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x40000000 0x20000000>;
49 };
50
51 reg_1p8v: regulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-1.8V";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <1800000>;
56 regulator-always-on;
57 regulator-boot-on;
58 };
59
60 reg_3p3v: regulator@1 {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-3.3V";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-always-on;
66 regulator-boot-on;
67 };
68
69 vmmc_sdhi0: regulator@2 {
70 compatible = "regulator-fixed";
71 regulator-name = "SDHI0 Vcc";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
75 enable-active-high;
76 };
77
78 vmmc_sdhi2: regulator@3 {
79 compatible = "regulator-fixed";
80 regulator-name = "SDHI2 Vcc";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 lan9220@10000000 {
88 compatible = "smsc,lan9220", "smsc,lan9115";
89 reg = <0x10000000 0x100>;
90 phy-mode = "mii";
91 interrupt-parent = <&irqpin0>;
92 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
93 reg-io-width = <4>;
94 smsc,irq-push-pull;
95 smsc,save-mac-address;
96 vddvario-supply = <&reg_1p8v>;
97 vdd33a-supply = <&reg_3p3v>;
98 };
99
100 leds {
101 compatible = "gpio-leds";
102 led1 {
103 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
104 label = "LED1";
105 };
106 led2 {
107 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
108 label = "LED2";
109 };
110 led3 {
111 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
112 label = "LED3";
113 };
114 led4 {
115 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
116 label = "LED4";
117 };
118 };
119
120 keyboard {
121 compatible = "gpio-keys";
122
123 back-key {
124 gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
125 linux,code = <KEY_BACK>;
126 label = "SW3";
127 };
128
129 right-key {
130 gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
131 linux,code = <KEY_RIGHT>;
132 label = "SW2-R";
133 };
134
135 left-key {
136 gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
137 linux,code = <KEY_LEFT>;
138 label = "SW2-L";
139 };
140
141 enter-key {
142 gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
143 linux,code = <KEY_ENTER>;
144 label = "SW2-P";
145 };
146
147 up-key {
148 gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
149 linux,code = <KEY_UP>;
150 label = "SW2-U";
151 };
152
153 down-key {
154 gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
155 linux,code = <KEY_DOWN>;
156 label = "SW2-D";
157 };
158
159 home-key {
160 gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
161 linux,code = <KEY_HOME>;
162 label = "SW1";
163 };
164 };
165
166 sound {
167 compatible = "simple-audio-card";
168 simple-audio-card,format = "left_j";
169 simple-audio-card,cpu {
170 sound-dai = <&sh_fsi2 0>;
171 };
172 simple-audio-card,codec {
173 sound-dai = <&ak4648>;
174 bitclock-master;
175 frame-master;
176 system-clock-frequency = <11289600>;
177 };
178 };
179};
180
181&cmt1 {
182 status = "okay";
183};
184
185&extal2_clk {
186 clock-frequency = <48000000>;
187};
188
189&i2c0 {
190 status = "okay";
191
192 compass@c {
193 compatible = "asahi-kasei,ak8975";
194 reg = <0x0c>;
195 interrupt-parent = <&irqpin3>;
196 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
197 };
198
199 ak4648: codec@12 {
200 compatible = "asahi-kasei,ak4648";
201 reg = <0x12>;
202 #sound-dai-cells = <0>;
203 };
204
205 accelerometer@1d {
206 compatible = "adi,adxl34x";
207 reg = <0x1d>;
208 interrupt-parent = <&irqpin3>;
209 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
210 <3 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
213 rtc@32 {
214 compatible = "ricoh,r2025sd";
215 reg = <0x32>;
216 };
217
218 as3711@40 {
219 compatible = "ams,as3711";
220 reg = <0x40>;
221
222 regulators {
223 vdd_dvfs: sd1 {
224 regulator-name = "1.315V CPU";
225 regulator-min-microvolt = <1050000>;
226 regulator-max-microvolt = <1350000>;
227 regulator-always-on;
228 regulator-boot-on;
229 };
230 sd2 {
231 regulator-name = "1.8V";
232 regulator-min-microvolt = <1800000>;
233 regulator-max-microvolt = <1800000>;
234 regulator-always-on;
235 regulator-boot-on;
236 };
237 sd4 {
238 regulator-name = "1.215V";
239 regulator-min-microvolt = <1215000>;
240 regulator-max-microvolt = <1235000>;
241 regulator-always-on;
242 regulator-boot-on;
243 };
244 ldo2 {
245 regulator-name = "2.8V CPU";
246 regulator-min-microvolt = <2800000>;
247 regulator-max-microvolt = <2800000>;
248 regulator-always-on;
249 regulator-boot-on;
250 };
251 ldo3 {
252 regulator-name = "3.0V CPU";
253 regulator-min-microvolt = <3000000>;
254 regulator-max-microvolt = <3000000>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258 ldo4 {
259 regulator-name = "2.8V";
260 regulator-min-microvolt = <2800000>;
261 regulator-max-microvolt = <2800000>;
262 regulator-always-on;
263 regulator-boot-on;
264 };
265 ldo5 {
266 regulator-name = "2.8V #2";
267 regulator-min-microvolt = <2800000>;
268 regulator-max-microvolt = <2800000>;
269 regulator-always-on;
270 regulator-boot-on;
271 };
272 ldo7 {
273 regulator-name = "1.15V CPU";
274 regulator-min-microvolt = <1150000>;
275 regulator-max-microvolt = <1150000>;
276 regulator-always-on;
277 regulator-boot-on;
278 };
279 ldo8 {
280 regulator-name = "1.15V CPU #2";
281 regulator-min-microvolt = <1150000>;
282 regulator-max-microvolt = <1150000>;
283 regulator-always-on;
284 regulator-boot-on;
285 };
286 };
287 };
288};
289
290&i2c1 {
291 status = "okay";
292
293 touchscreen@55 {
294 compatible = "sitronix,st1232";
295 reg = <0x55>;
296 interrupt-parent = <&irqpin1>;
297 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
298 };
299};
300
301&i2c3 {
302 pinctrl-0 = <&i2c3_pins>;
303 pinctrl-names = "default";
304 status = "okay";
305
306 pcf8575: gpio@20 {
307 compatible = "nxp,pcf8575";
308 reg = <0x20>;
309 interrupt-parent = <&irqpin2>;
310 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
311 gpio-controller;
312 #gpio-cells = <2>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
315 };
316};
317
318&mmcif {
319 pinctrl-0 = <&mmcif_pins>;
320 pinctrl-names = "default";
321
322 bus-width = <8>;
323 vmmc-supply = <&reg_1p8v>;
324 status = "okay";
325};
326
327&pfc {
328 i2c3_pins: i2c3 {
329 renesas,groups = "i2c3_1";
330 renesas,function = "i2c3";
331 };
332
333 mmcif_pins: mmc {
334 mux {
335 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
336 renesas,function = "mmc0";
337 };
338 cfg {
339 renesas,groups = "mmc0_data8_0";
340 renesas,pins = "PORT279";
341 bias-pull-up;
342 };
343 };
344
345 scifa4_pins: serial4 {
346 renesas,groups = "scifa4_data", "scifa4_ctrl";
347 renesas,function = "scifa4";
348 };
349
350 sdhi0_pins: sd0 {
351 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
352 renesas,function = "sdhi0";
353 };
354
355 sdhi2_pins: sd2 {
356 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
357 renesas,function = "sdhi2";
358 };
359
360 fsia_pins: sounda {
361 renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
362 "fsia_data_in", "fsia_data_out";
363 renesas,function = "fsia";
364 };
365};
366
367&scifa4 {
368 pinctrl-0 = <&scifa4_pins>;
369 pinctrl-names = "default";
370
371 status = "okay";
372};
373
374&sdhi0 {
375 pinctrl-0 = <&sdhi0_pins>;
376 pinctrl-names = "default";
377
378 vmmc-supply = <&vmmc_sdhi0>;
379 bus-width = <4>;
380 status = "okay";
381};
382
383&sdhi2 {
384 pinctrl-0 = <&sdhi2_pins>;
385 pinctrl-names = "default";
386
387 vmmc-supply = <&vmmc_sdhi2>;
388 bus-width = <4>;
389 broken-cd;
390 status = "okay";
391};
392
393&sh_fsi2 {
394 pinctrl-0 = <&fsia_pins>;
395 pinctrl-names = "default";
396
397 status = "okay";
398};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index e7dae01933a5..022ba505f573 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -1,6 +1,9 @@
1/* 1/*
2 * Device Tree Source for the KZM-A9-GT board 2 * Device Tree Source for the KZM-A9-GT board
3 * 3 *
4 * Copyright (C) 2012 Horms Solutions Ltd.
5 *
6 * Based on sh73a0-kzm9g.dts
4 * Copyright (C) 2012 Renesas Solutions Corp. 7 * Copyright (C) 2012 Renesas Solutions Corp.
5 * 8 *
6 * This file is licensed under the terms of the GNU General Public License 9 * This file is licensed under the terms of the GNU General Public License
@@ -10,17 +13,388 @@
10 13
11/dts-v1/; 14/dts-v1/;
12#include "sh73a0.dtsi" 15#include "sh73a0.dtsi"
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
13 19
14/ { 20/ {
15 model = "KZM-A9-GT"; 21 model = "KZM-A9-GT";
16 compatible = "renesas,kzm9g", "renesas,sh73a0"; 22 compatible = "renesas,kzm9g", "renesas,sh73a0";
17 23
24 aliases {
25 serial4 = &scifa4;
26 };
27
28 cpus {
29 cpu@0 {
30 cpu0-supply = <&vdd_dvfs>;
31 operating-points = <
32 /* kHz uV */
33 1196000 1315000
34 598000 1175000
35 398667 1065000
36 >;
37 voltage-tolerance = <1>; /* 1% */
38 };
39 };
40
18 chosen { 41 chosen {
19 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; 42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
43 stdout-path = &scifa4;
20 }; 44 };
21 45
22 memory { 46 memory {
23 device_type = "memory"; 47 device_type = "memory";
24 reg = <0x40000000 0x20000000>; 48 reg = <0x40000000 0x20000000>;
25 }; 49 };
50
51 reg_1p8v: regulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-1.8V";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <1800000>;
56 regulator-always-on;
57 regulator-boot-on;
58 };
59
60 reg_3p3v: regulator@1 {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-3.3V";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-always-on;
66 regulator-boot-on;
67 };
68
69 vmmc_sdhi0: regulator@2 {
70 compatible = "regulator-fixed";
71 regulator-name = "SDHI0 Vcc";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
75 enable-active-high;
76 };
77
78 vmmc_sdhi2: regulator@3 {
79 compatible = "regulator-fixed";
80 regulator-name = "SDHI2 Vcc";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 leds {
88 compatible = "gpio-leds";
89 led1 {
90 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
91 label = "LED1";
92 };
93 led2 {
94 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
95 label = "LED2";
96 };
97 led3 {
98 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
99 label = "LED3";
100 };
101 led4 {
102 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
103 label = "LED4";
104 };
105 };
106
107 keyboard {
108 compatible = "gpio-keys";
109
110 back-key {
111 gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
112 linux,code = <KEY_BACK>;
113 label = "SW3";
114 };
115
116 right-key {
117 gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
118 linux,code = <KEY_RIGHT>;
119 label = "SW2-R";
120 };
121
122 left-key {
123 gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
124 linux,code = <KEY_LEFT>;
125 label = "SW2-L";
126 };
127
128 enter-key {
129 gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
130 linux,code = <KEY_ENTER>;
131 label = "SW2-P";
132 };
133
134 up-key {
135 gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
136 linux,code = <KEY_UP>;
137 label = "SW2-U";
138 };
139
140 down-key {
141 gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
142 linux,code = <KEY_DOWN>;
143 label = "SW2-D";
144 };
145
146 home-key {
147 gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
148 linux,code = <KEY_HOME>;
149 label = "SW1";
150 };
151 };
152
153 sound {
154 compatible = "simple-audio-card";
155 simple-audio-card,format = "left_j";
156 simple-audio-card,cpu {
157 sound-dai = <&sh_fsi2 0>;
158 };
159 simple-audio-card,codec {
160 sound-dai = <&ak4648>;
161 bitclock-master;
162 frame-master;
163 system-clock-frequency = <11289600>;
164 };
165 };
166};
167
168&bsc {
169 ethernet@10000000 {
170 compatible = "smsc,lan9220", "smsc,lan9115";
171 reg = <0x10000000 0x100>;
172 phy-mode = "mii";
173 interrupt-parent = <&irqpin0>;
174 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
175 reg-io-width = <4>;
176 smsc,irq-push-pull;
177 smsc,save-mac-address;
178 vddvario-supply = <&reg_1p8v>;
179 vdd33a-supply = <&reg_3p3v>;
180 };
181};
182
183&cmt1 {
184 status = "okay";
185};
186
187&extal2_clk {
188 clock-frequency = <48000000>;
189};
190
191&i2c0 {
192 status = "okay";
193
194 compass@c {
195 compatible = "asahi-kasei,ak8975";
196 reg = <0x0c>;
197 interrupt-parent = <&irqpin3>;
198 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
199 };
200
201 ak4648: codec@12 {
202 compatible = "asahi-kasei,ak4648";
203 reg = <0x12>;
204 #sound-dai-cells = <0>;
205 };
206
207 accelerometer@1d {
208 compatible = "adi,adxl34x";
209 reg = <0x1d>;
210 interrupt-parent = <&irqpin3>;
211 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
212 <3 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
215 rtc@32 {
216 compatible = "ricoh,r2025sd";
217 reg = <0x32>;
218 };
219
220 as3711@40 {
221 compatible = "ams,as3711";
222 reg = <0x40>;
223
224 regulators {
225 vdd_dvfs: sd1 {
226 regulator-name = "1.315V CPU";
227 regulator-min-microvolt = <1050000>;
228 regulator-max-microvolt = <1350000>;
229 regulator-always-on;
230 regulator-boot-on;
231 };
232 sd2 {
233 regulator-name = "1.8V";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239 sd4 {
240 regulator-name = "1.215V";
241 regulator-min-microvolt = <1215000>;
242 regulator-max-microvolt = <1235000>;
243 regulator-always-on;
244 regulator-boot-on;
245 };
246 ldo2 {
247 regulator-name = "2.8V CPU";
248 regulator-min-microvolt = <2800000>;
249 regulator-max-microvolt = <2800000>;
250 regulator-always-on;
251 regulator-boot-on;
252 };
253 ldo3 {
254 regulator-name = "3.0V CPU";
255 regulator-min-microvolt = <3000000>;
256 regulator-max-microvolt = <3000000>;
257 regulator-always-on;
258 regulator-boot-on;
259 };
260 ldo4 {
261 regulator-name = "2.8V";
262 regulator-min-microvolt = <2800000>;
263 regulator-max-microvolt = <2800000>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267 ldo5 {
268 regulator-name = "2.8V #2";
269 regulator-min-microvolt = <2800000>;
270 regulator-max-microvolt = <2800000>;
271 regulator-always-on;
272 regulator-boot-on;
273 };
274 ldo7 {
275 regulator-name = "1.15V CPU";
276 regulator-min-microvolt = <1150000>;
277 regulator-max-microvolt = <1150000>;
278 regulator-always-on;
279 regulator-boot-on;
280 };
281 ldo8 {
282 regulator-name = "1.15V CPU #2";
283 regulator-min-microvolt = <1150000>;
284 regulator-max-microvolt = <1150000>;
285 regulator-always-on;
286 regulator-boot-on;
287 };
288 };
289 };
290};
291
292&i2c1 {
293 status = "okay";
294
295 touchscreen@55 {
296 compatible = "sitronix,st1232";
297 reg = <0x55>;
298 interrupt-parent = <&irqpin1>;
299 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
300 };
301};
302
303&i2c3 {
304 pinctrl-0 = <&i2c3_pins>;
305 pinctrl-names = "default";
306 status = "okay";
307
308 pcf8575: gpio@20 {
309 compatible = "nxp,pcf8575";
310 reg = <0x20>;
311 interrupt-parent = <&irqpin2>;
312 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318};
319
320&mmcif {
321 pinctrl-0 = <&mmcif_pins>;
322 pinctrl-names = "default";
323
324 bus-width = <8>;
325 vmmc-supply = <&reg_1p8v>;
326 status = "okay";
327};
328
329&pfc {
330 i2c3_pins: i2c3 {
331 renesas,groups = "i2c3_1";
332 renesas,function = "i2c3";
333 };
334
335 mmcif_pins: mmc {
336 mux {
337 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
338 renesas,function = "mmc0";
339 };
340 cfg {
341 renesas,groups = "mmc0_data8_0";
342 renesas,pins = "PORT279";
343 bias-pull-up;
344 };
345 };
346
347 scifa4_pins: serial4 {
348 renesas,groups = "scifa4_data", "scifa4_ctrl";
349 renesas,function = "scifa4";
350 };
351
352 sdhi0_pins: sd0 {
353 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
354 renesas,function = "sdhi0";
355 };
356
357 sdhi2_pins: sd2 {
358 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
359 renesas,function = "sdhi2";
360 };
361
362 fsia_pins: sounda {
363 renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
364 "fsia_data_in", "fsia_data_out";
365 renesas,function = "fsia";
366 };
367};
368
369&scifa4 {
370 pinctrl-0 = <&scifa4_pins>;
371 pinctrl-names = "default";
372
373 status = "okay";
374};
375
376&sdhi0 {
377 pinctrl-0 = <&sdhi0_pins>;
378 pinctrl-names = "default";
379
380 vmmc-supply = <&vmmc_sdhi0>;
381 bus-width = <4>;
382 status = "okay";
383};
384
385&sdhi2 {
386 pinctrl-0 = <&sdhi2_pins>;
387 pinctrl-names = "default";
388
389 vmmc-supply = <&vmmc_sdhi2>;
390 bus-width = <4>;
391 broken-cd;
392 status = "okay";
393};
394
395&sh_fsi2 {
396 pinctrl-0 = <&fsia_pins>;
397 pinctrl-names = "default";
398
399 status = "okay";
26}; 400};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index ab319b73e282..45b539ce4d35 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -11,6 +11,7 @@
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/clock/sh73a0-clock.h> 13#include <dt-bindings/clock/sh73a0-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
15 16
16/ { 17/ {
@@ -26,15 +27,24 @@
26 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
27 reg = <0>; 28 reg = <0>;
28 clock-frequency = <1196000000>; 29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
29 }; 31 };
30 cpu@1 { 32 cpu@1 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
33 reg = <1>; 35 reg = <1>;
34 clock-frequency = <1196000000>; 36 clock-frequency = <1196000000>;
37 power-domains = <&pd_a2sl>;
35 }; 38 };
36 }; 39 };
37 40
41 timer@f0000600 {
42 compatible = "arm,cortex-a9-twd-timer";
43 reg = <0xf0000600 0x20>;
44 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
45 clocks = <&twd_clk>;
46 };
47
38 gic: interrupt-controller@f0001000 { 48 gic: interrupt-controller@f0001000 {
39 compatible = "arm,cortex-a9-gic"; 49 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>; 50 #interrupt-cells = <3>;
@@ -49,6 +59,7 @@
49 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, 59 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
50 <0 38 IRQ_TYPE_LEVEL_HIGH>; 60 <0 38 IRQ_TYPE_LEVEL_HIGH>;
51 interrupt-names = "sec", "temp"; 61 interrupt-names = "sec", "temp";
62 power-domains = <&pd_a4bc1>;
52 }; 63 };
53 64
54 sbsc1: memory-controller@fe400000 { 65 sbsc1: memory-controller@fe400000 {
@@ -57,6 +68,7 @@
57 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, 68 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
58 <0 36 IRQ_TYPE_LEVEL_HIGH>; 69 <0 36 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-names = "sec", "temp"; 70 interrupt-names = "sec", "temp";
71 power-domains = <&pd_a4bc0>;
60 }; 72 };
61 73
62 pmu { 74 pmu {
@@ -69,11 +81,12 @@
69 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; 81 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
70 reg = <0xe6138000 0x200>; 82 reg = <0xe6138000 0x200>;
71 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; 83 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
85 clock-names = "fck";
86 power-domains = <&pd_c5>;
72 87
73 renesas,channels-mask = <0x3f>; 88 renesas,channels-mask = <0x3f>;
74 89
75 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
76 clock-names = "fck";
77 status = "disabled"; 90 status = "disabled";
78 }; 91 };
79 92
@@ -95,6 +108,7 @@
95 0 7 IRQ_TYPE_LEVEL_HIGH 108 0 7 IRQ_TYPE_LEVEL_HIGH
96 0 8 IRQ_TYPE_LEVEL_HIGH>; 109 0 8 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
111 power-domains = <&pd_a4s>;
98 control-parent; 112 control-parent;
99 }; 113 };
100 114
@@ -116,6 +130,7 @@
116 0 15 IRQ_TYPE_LEVEL_HIGH 130 0 15 IRQ_TYPE_LEVEL_HIGH
117 0 16 IRQ_TYPE_LEVEL_HIGH>; 131 0 16 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
133 power-domains = <&pd_a4s>;
119 control-parent; 134 control-parent;
120 }; 135 };
121 136
@@ -137,6 +152,7 @@
137 0 23 IRQ_TYPE_LEVEL_HIGH 152 0 23 IRQ_TYPE_LEVEL_HIGH
138 0 24 IRQ_TYPE_LEVEL_HIGH>; 153 0 24 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
155 power-domains = <&pd_a4s>;
140 control-parent; 156 control-parent;
141 }; 157 };
142 158
@@ -158,6 +174,7 @@
158 0 31 IRQ_TYPE_LEVEL_HIGH 174 0 31 IRQ_TYPE_LEVEL_HIGH
159 0 32 IRQ_TYPE_LEVEL_HIGH>; 175 0 32 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
177 power-domains = <&pd_a4s>;
161 control-parent; 178 control-parent;
162 }; 179 };
163 180
@@ -171,6 +188,7 @@
171 0 169 IRQ_TYPE_LEVEL_HIGH 188 0 169 IRQ_TYPE_LEVEL_HIGH
172 0 170 IRQ_TYPE_LEVEL_HIGH>; 189 0 170 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&mstp1_clks SH73A0_CLK_IIC0>; 190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
191 power-domains = <&pd_a3sp>;
174 status = "disabled"; 192 status = "disabled";
175 }; 193 };
176 194
@@ -184,6 +202,7 @@
184 0 53 IRQ_TYPE_LEVEL_HIGH 202 0 53 IRQ_TYPE_LEVEL_HIGH
185 0 54 IRQ_TYPE_LEVEL_HIGH>; 203 0 54 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&mstp3_clks SH73A0_CLK_IIC1>; 204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
205 power-domains = <&pd_a3sp>;
187 status = "disabled"; 206 status = "disabled";
188 }; 207 };
189 208
@@ -197,6 +216,7 @@
197 0 173 IRQ_TYPE_LEVEL_HIGH 216 0 173 IRQ_TYPE_LEVEL_HIGH
198 0 174 IRQ_TYPE_LEVEL_HIGH>; 217 0 174 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&mstp0_clks SH73A0_CLK_IIC2>; 218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
219 power-domains = <&pd_a3sp>;
200 status = "disabled"; 220 status = "disabled";
201 }; 221 };
202 222
@@ -210,6 +230,7 @@
210 0 185 IRQ_TYPE_LEVEL_HIGH 230 0 185 IRQ_TYPE_LEVEL_HIGH
211 0 186 IRQ_TYPE_LEVEL_HIGH>; 231 0 186 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&mstp4_clks SH73A0_CLK_IIC3>; 232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
233 power-domains = <&pd_a3sp>;
213 status = "disabled"; 234 status = "disabled";
214 }; 235 };
215 236
@@ -223,6 +244,7 @@
223 0 189 IRQ_TYPE_LEVEL_HIGH 244 0 189 IRQ_TYPE_LEVEL_HIGH
224 0 190 IRQ_TYPE_LEVEL_HIGH>; 245 0 190 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&mstp4_clks SH73A0_CLK_IIC4>; 246 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
247 power-domains = <&pd_c5>;
226 status = "disabled"; 248 status = "disabled";
227 }; 249 };
228 250
@@ -232,6 +254,7 @@
232 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 254 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
233 0 141 IRQ_TYPE_LEVEL_HIGH>; 255 0 141 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; 256 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
257 power-domains = <&pd_a3sp>;
235 reg-io-width = <4>; 258 reg-io-width = <4>;
236 status = "disabled"; 259 status = "disabled";
237 }; 260 };
@@ -243,6 +266,7 @@
243 0 84 IRQ_TYPE_LEVEL_HIGH 266 0 84 IRQ_TYPE_LEVEL_HIGH
244 0 85 IRQ_TYPE_LEVEL_HIGH>; 267 0 85 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; 268 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
269 power-domains = <&pd_a3sp>;
246 cap-sd-highspeed; 270 cap-sd-highspeed;
247 status = "disabled"; 271 status = "disabled";
248 }; 272 };
@@ -254,6 +278,7 @@
254 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 278 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
255 0 89 IRQ_TYPE_LEVEL_HIGH>; 279 0 89 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; 280 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
281 power-domains = <&pd_a3sp>;
257 toshiba,mmc-wrprotect-disable; 282 toshiba,mmc-wrprotect-disable;
258 cap-sd-highspeed; 283 cap-sd-highspeed;
259 status = "disabled"; 284 status = "disabled";
@@ -265,6 +290,7 @@
265 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 290 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
266 0 105 IRQ_TYPE_LEVEL_HIGH>; 291 0 105 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; 292 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
293 power-domains = <&pd_a3sp>;
268 toshiba,mmc-wrprotect-disable; 294 toshiba,mmc-wrprotect-disable;
269 cap-sd-highspeed; 295 cap-sd-highspeed;
270 status = "disabled"; 296 status = "disabled";
@@ -276,6 +302,7 @@
276 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 302 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; 303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
278 clock-names = "sci_ick"; 304 clock-names = "sci_ick";
305 power-domains = <&pd_a3sp>;
279 status = "disabled"; 306 status = "disabled";
280 }; 307 };
281 308
@@ -285,6 +312,7 @@
285 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 312 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; 313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
287 clock-names = "sci_ick"; 314 clock-names = "sci_ick";
315 power-domains = <&pd_a3sp>;
288 status = "disabled"; 316 status = "disabled";
289 }; 317 };
290 318
@@ -294,6 +322,7 @@
294 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; 323 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
296 clock-names = "sci_ick"; 324 clock-names = "sci_ick";
325 power-domains = <&pd_a3sp>;
297 status = "disabled"; 326 status = "disabled";
298 }; 327 };
299 328
@@ -303,6 +332,7 @@
303 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 332 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; 333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
305 clock-names = "sci_ick"; 334 clock-names = "sci_ick";
335 power-domains = <&pd_a3sp>;
306 status = "disabled"; 336 status = "disabled";
307 }; 337 };
308 338
@@ -312,6 +342,7 @@
312 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; 343 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
314 clock-names = "sci_ick"; 344 clock-names = "sci_ick";
345 power-domains = <&pd_a3sp>;
315 status = "disabled"; 346 status = "disabled";
316 }; 347 };
317 348
@@ -321,6 +352,7 @@
321 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; 353 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
323 clock-names = "sci_ick"; 354 clock-names = "sci_ick";
355 power-domains = <&pd_a3sp>;
324 status = "disabled"; 356 status = "disabled";
325 }; 357 };
326 358
@@ -330,6 +362,7 @@
330 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 362 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; 363 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
332 clock-names = "sci_ick"; 364 clock-names = "sci_ick";
365 power-domains = <&pd_a3sp>;
333 status = "disabled"; 366 status = "disabled";
334 }; 367 };
335 368
@@ -339,6 +372,7 @@
339 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 372 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; 373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
341 clock-names = "sci_ick"; 374 clock-names = "sci_ick";
375 power-domains = <&pd_a3sp>;
342 status = "disabled"; 376 status = "disabled";
343 }; 377 };
344 378
@@ -348,6 +382,7 @@
348 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; 383 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
350 clock-names = "sci_ick"; 384 clock-names = "sci_ick";
385 power-domains = <&pd_a3sp>;
351 status = "disabled"; 386 status = "disabled";
352 }; 387 };
353 388
@@ -366,6 +401,117 @@
366 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 401 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
367 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 402 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
368 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 403 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
404 power-domains = <&pd_c5>;
405 };
406
407 sysc: system-controller@e6180000 {
408 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
409 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
410
411 pm-domains {
412 pd_c5: c5 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 #power-domain-cells = <0>;
416
417 pd_c4: c4@0 {
418 reg = <0>;
419 #power-domain-cells = <0>;
420 };
421
422 pd_d4: d4@1 {
423 reg = <1>;
424 #power-domain-cells = <0>;
425 };
426
427 pd_a4bc0: a4bc0@4 {
428 reg = <4>;
429 #power-domain-cells = <0>;
430 };
431
432 pd_a4bc1: a4bc1@5 {
433 reg = <5>;
434 #power-domain-cells = <0>;
435 };
436
437 pd_a4lc0: a4lc0@6 {
438 reg = <6>;
439 #power-domain-cells = <0>;
440 };
441
442 pd_a4lc1: a4lc1@7 {
443 reg = <7>;
444 #power-domain-cells = <0>;
445 };
446
447 pd_a4mp: a4mp@8 {
448 reg = <8>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 #power-domain-cells = <0>;
452
453 pd_a3mp: a3mp@9 {
454 reg = <9>;
455 #power-domain-cells = <0>;
456 };
457
458 pd_a3vc: a3vc@10 {
459 reg = <10>;
460 #power-domain-cells = <0>;
461 };
462 };
463
464 pd_a4rm: a4rm@12 {
465 reg = <12>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 #power-domain-cells = <0>;
469
470 pd_a3r: a3r@13 {
471 reg = <13>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 #power-domain-cells = <0>;
475
476 pd_a2rv: a2rv@14 {
477 reg = <14>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
481 };
482 };
483 };
484
485 pd_a4s: a4s@16 {
486 reg = <16>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 #power-domain-cells = <0>;
490
491 pd_a3sp: a3sp@17 {
492 reg = <17>;
493 #power-domain-cells = <0>;
494 };
495
496 pd_a3sg: a3sg@18 {
497 reg = <18>;
498 #power-domain-cells = <0>;
499 };
500
501 pd_a3sm: a3sm@19 {
502 reg = <19>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 #power-domain-cells = <0>;
506
507 pd_a2sl: a2sl@20 {
508 reg = <20>;
509 #power-domain-cells = <0>;
510 };
511 };
512 };
513 };
514 };
369 }; 515 };
370 516
371 sh_fsi2: sound@ec230000 { 517 sh_fsi2: sound@ec230000 {
@@ -373,9 +519,22 @@
373 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; 519 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
374 reg = <0xec230000 0x400>; 520 reg = <0xec230000 0x400>;
375 interrupts = <0 146 0x4>; 521 interrupts = <0 146 0x4>;
522 power-domains = <&pd_a4mp>;
376 status = "disabled"; 523 status = "disabled";
377 }; 524 };
378 525
526 bsc: bus@fec10000 {
527 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
528 "simple-pm-bus";
529 #address-cells = <1>;
530 #size-cells = <1>;
531 ranges = <0 0 0x20000000>;
532 reg = <0xfec10000 0x400>;
533 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&zb_clk>;
535 power-domains = <&pd_a4s>;
536 };
537
379 clocks { 538 clocks {
380 #address-cells = <1>; 539 #address-cells = <1>;
381 #size-cells = <1>; 540 #size-cells = <1>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 19:25:19 -0400