dmaengine: dw: define DW_DMA_MAX_NR_MASTERS

Instead of using magic number in the code the patch provides
DW_DMA_MAX_NR_MASTERS constant.

While here, restrict the reading of data width array by amount of the actual
number of AHB masters.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index a6eb5436d26d..40accc87e3a2 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -117,7 +117,7 @@
                         chan_priority = <1>;
                         block_size = <0xfff>;
                         dma-masters = <2>;
-                        data_width = <3 3 0 0>;
+                        data_width = <3 3>;
                 };
 
                 dma@eb000000 {
@@ -133,7 +133,7 @@
                         chan_allocation_order = <1>;
                         chan_priority = <1>;
                         block_size = <0xfff>;
-                        data_width = <3 3 0 0>;
+                        data_width = <3 3>;
                 };
 
                 fsmc: flash@b0000000 {