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authorMurali Karicheri <m-karicheri2@ti.com>2014-02-24 10:44:07 -0500
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2014-02-26 10:06:56 -0500
commita206767629046c9978b06f78d1589a75c2629201 (patch)
tree551f5af8c619204103df1445ce4a100a1f78d4c3 /arch/arm/boot/dts
parentf0a289e5086c525eb8ed835ba2d1c5a8a16c04f0 (diff)
ARM: dts: keystone: preparatory patch to support K2L and K2E SOCs
Current keystone.dtsi includes SoC specific definitions for K2HK SoCs. In order to support two addition keystone devices, k2 Edison and K2 Lamarr and corresponding EVMs, This patch restructure the dts files for the following:- - All clock nodes that are only available in k2hk SoC are moved from keystone-clocks.dtsi to a new k2hk-clocks.dtsi include file - The CPU nodes are now part of the soc specific k2hk.dtsi. - Change the compatibility string to ti,k2hk-evm and change the model name accordingly - Finally include k2hk-clocks.dtsi in k2hk.dtsi and that in k2hk-evm.dts Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/k2hk-clocks.dtsi426
-rw-r--r--arch/arm/boot/dts/k2hk-evm.dts6
-rw-r--r--arch/arm/boot/dts/k2hk.dtsi46
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi405
-rw-r--r--arch/arm/boot/dts/keystone.dtsi31
5 files changed, 476 insertions, 438 deletions
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi
new file mode 100644
index 000000000000..a71aa2996321
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -0,0 +1,426 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Kepler/Hawking SoC clock nodes
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 armpllclk: armpllclk@2620370 {
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
15 clocks = <&refclkarm>;
16 clock-output-names = "arm-pll-clk";
17 reg = <0x02620370 4>;
18 reg-names = "control";
19 };
20
21 mainpllclk: mainpllclk@2310110 {
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
24 clocks = <&refclksys>;
25 reg = <0x02620350 4>, <0x02310110 4>;
26 reg-names = "control", "multiplier";
27 fixed-postdiv = <2>;
28 };
29
30 papllclk: papllclk@2620358 {
31 #clock-cells = <0>;
32 compatible = "ti,keystone,pll-clock";
33 clocks = <&refclkpass>;
34 clock-output-names = "pa-pll-clk";
35 reg = <0x02620358 4>;
36 reg-names = "control";
37 };
38
39 ddr3apllclk: ddr3apllclk@2620360 {
40 #clock-cells = <0>;
41 compatible = "ti,keystone,pll-clock";
42 clocks = <&refclkddr3a>;
43 clock-output-names = "ddr-3a-pll-clk";
44 reg = <0x02620360 4>;
45 reg-names = "control";
46 };
47
48 ddr3bpllclk: ddr3bpllclk@2620368 {
49 #clock-cells = <0>;
50 compatible = "ti,keystone,pll-clock";
51 clocks = <&refclkddr3b>;
52 clock-output-names = "ddr-3b-pll-clk";
53 reg = <0x02620368 4>;
54 reg-names = "control";
55 };
56
57 clktsip: clktsip {
58 #clock-cells = <0>;
59 compatible = "ti,keystone,psc-clock";
60 clocks = <&chipclk16>;
61 clock-output-names = "tsip";
62 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
63 reg-names = "control", "domain";
64 domain-id = <0>;
65 };
66
67 clksrio: clksrio {
68 #clock-cells = <0>;
69 compatible = "ti,keystone,psc-clock";
70 clocks = <&chipclk1rstiso13>;
71 clock-output-names = "srio";
72 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
73 reg-names = "control", "domain";
74 domain-id = <4>;
75 };
76
77 clkhyperlink0: clkhyperlink0 {
78 #clock-cells = <0>;
79 compatible = "ti,keystone,psc-clock";
80 clocks = <&chipclk12>;
81 clock-output-names = "hyperlink-0";
82 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
83 reg-names = "control", "domain";
84 domain-id = <5>;
85 };
86
87 clkgem1: clkgem1 {
88 #clock-cells = <0>;
89 compatible = "ti,keystone,psc-clock";
90 clocks = <&chipclk1>;
91 clock-output-names = "gem1";
92 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
93 reg-names = "control", "domain";
94 domain-id = <9>;
95 };
96
97 clkgem2: clkgem2 {
98 #clock-cells = <0>;
99 compatible = "ti,keystone,psc-clock";
100 clocks = <&chipclk1>;
101 clock-output-names = "gem2";
102 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
103 reg-names = "control", "domain";
104 domain-id = <10>;
105 };
106
107 clkgem3: clkgem3 {
108 #clock-cells = <0>;
109 compatible = "ti,keystone,psc-clock";
110 clocks = <&chipclk1>;
111 clock-output-names = "gem3";
112 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
113 reg-names = "control", "domain";
114 domain-id = <11>;
115 };
116
117 clkgem4: clkgem4 {
118 #clock-cells = <0>;
119 compatible = "ti,keystone,psc-clock";
120 clocks = <&chipclk1>;
121 clock-output-names = "gem4";
122 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
123 reg-names = "control", "domain";
124 domain-id = <12>;
125 };
126
127 clkgem5: clkgem5 {
128 #clock-cells = <0>;
129 compatible = "ti,keystone,psc-clock";
130 clocks = <&chipclk1>;
131 clock-output-names = "gem5";
132 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
133 reg-names = "control", "domain";
134 domain-id = <13>;
135 };
136
137 clkgem6: clkgem6 {
138 #clock-cells = <0>;
139 compatible = "ti,keystone,psc-clock";
140 clocks = <&chipclk1>;
141 clock-output-names = "gem6";
142 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
143 reg-names = "control", "domain";
144 domain-id = <14>;
145 };
146
147 clkgem7: clkgem7 {
148 #clock-cells = <0>;
149 compatible = "ti,keystone,psc-clock";
150 clocks = <&chipclk1>;
151 clock-output-names = "gem7";
152 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
153 reg-names = "control", "domain";
154 domain-id = <15>;
155 };
156
157 clkddr31: clkddr31 {
158 #clock-cells = <0>;
159 compatible = "ti,keystone,psc-clock";
160 clocks = <&chipclk13>;
161 clock-output-names = "ddr3-1";
162 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
163 reg-names = "control", "domain";
164 domain-id = <16>;
165 };
166
167 clktac: clktac {
168 #clock-cells = <0>;
169 compatible = "ti,keystone,psc-clock";
170 clocks = <&chipclk13>;
171 clock-output-names = "tac";
172 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
173 reg-names = "control", "domain";
174 domain-id = <17>;
175 };
176
177 clkrac01: clkrac01 {
178 #clock-cells = <0>;
179 compatible = "ti,keystone,psc-clock";
180 clocks = <&chipclk13>;
181 clock-output-names = "rac-01";
182 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
183 reg-names = "control", "domain";
184 domain-id = <17>;
185 };
186
187 clkrac23: clkrac23 {
188 #clock-cells = <0>;
189 compatible = "ti,keystone,psc-clock";
190 clocks = <&chipclk13>;
191 clock-output-names = "rac-23";
192 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
193 reg-names = "control", "domain";
194 domain-id = <18>;
195 };
196
197 clkfftc0: clkfftc0 {
198 #clock-cells = <0>;
199 compatible = "ti,keystone,psc-clock";
200 clocks = <&chipclk13>;
201 clock-output-names = "fftc-0";
202 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
203 reg-names = "control", "domain";
204 domain-id = <19>;
205 };
206
207 clkfftc1: clkfftc1 {
208 #clock-cells = <0>;
209 compatible = "ti,keystone,psc-clock";
210 clocks = <&chipclk13>;
211 clock-output-names = "fftc-1";
212 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
213 reg-names = "control", "domain";
214 domain-id = <19>;
215 };
216
217 clkfftc2: clkfftc2 {
218 #clock-cells = <0>;
219 compatible = "ti,keystone,psc-clock";
220 clocks = <&chipclk13>;
221 clock-output-names = "fftc-2";
222 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
223 reg-names = "control", "domain";
224 domain-id = <20>;
225 };
226
227 clkfftc3: clkfftc3 {
228 #clock-cells = <0>;
229 compatible = "ti,keystone,psc-clock";
230 clocks = <&chipclk13>;
231 clock-output-names = "fftc-3";
232 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
233 reg-names = "control", "domain";
234 domain-id = <20>;
235 };
236
237 clkfftc4: clkfftc4 {
238 #clock-cells = <0>;
239 compatible = "ti,keystone,psc-clock";
240 clocks = <&chipclk13>;
241 clock-output-names = "fftc-4";
242 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
243 reg-names = "control", "domain";
244 domain-id = <20>;
245 };
246
247 clkfftc5: clkfftc5 {
248 #clock-cells = <0>;
249 compatible = "ti,keystone,psc-clock";
250 clocks = <&chipclk13>;
251 clock-output-names = "fftc-5";
252 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
253 reg-names = "control", "domain";
254 domain-id = <20>;
255 };
256
257 clkaif: clkaif {
258 #clock-cells = <0>;
259 compatible = "ti,keystone,psc-clock";
260 clocks = <&chipclk13>;
261 clock-output-names = "aif";
262 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
263 reg-names = "control", "domain";
264 domain-id = <21>;
265 };
266
267 clktcp3d0: clktcp3d0 {
268 #clock-cells = <0>;
269 compatible = "ti,keystone,psc-clock";
270 clocks = <&chipclk13>;
271 clock-output-names = "tcp3d-0";
272 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
273 reg-names = "control", "domain";
274 domain-id = <22>;
275 };
276
277 clktcp3d1: clktcp3d1 {
278 #clock-cells = <0>;
279 compatible = "ti,keystone,psc-clock";
280 clocks = <&chipclk13>;
281 clock-output-names = "tcp3d-1";
282 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
283 reg-names = "control", "domain";
284 domain-id = <22>;
285 };
286
287 clktcp3d2: clktcp3d2 {
288 #clock-cells = <0>;
289 compatible = "ti,keystone,psc-clock";
290 clocks = <&chipclk13>;
291 clock-output-names = "tcp3d-2";
292 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
293 reg-names = "control", "domain";
294 domain-id = <23>;
295 };
296
297 clktcp3d3: clktcp3d3 {
298 #clock-cells = <0>;
299 compatible = "ti,keystone,psc-clock";
300 clocks = <&chipclk13>;
301 clock-output-names = "tcp3d-3";
302 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
303 reg-names = "control", "domain";
304 domain-id = <23>;
305 };
306
307 clkvcp0: clkvcp0 {
308 #clock-cells = <0>;
309 compatible = "ti,keystone,psc-clock";
310 clocks = <&chipclk13>;
311 clock-output-names = "vcp-0";
312 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
313 reg-names = "control", "domain";
314 domain-id = <24>;
315 };
316
317 clkvcp1: clkvcp1 {
318 #clock-cells = <0>;
319 compatible = "ti,keystone,psc-clock";
320 clocks = <&chipclk13>;
321 clock-output-names = "vcp-1";
322 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
323 reg-names = "control", "domain";
324 domain-id = <24>;
325 };
326
327 clkvcp2: clkvcp2 {
328 #clock-cells = <0>;
329 compatible = "ti,keystone,psc-clock";
330 clocks = <&chipclk13>;
331 clock-output-names = "vcp-2";
332 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
333 reg-names = "control", "domain";
334 domain-id = <24>;
335 };
336
337 clkvcp3: clkvcp3 {
338 #clock-cells = <0>;
339 compatible = "ti,keystone,psc-clock";
340 clocks = <&chipclk13>;
341 clock-output-names = "vcp-3";
342 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
343 reg-names = "control", "domain";
344 domain-id = <24>;
345 };
346
347 clkvcp4: clkvcp4 {
348 #clock-cells = <0>;
349 compatible = "ti,keystone,psc-clock";
350 clocks = <&chipclk13>;
351 clock-output-names = "vcp-4";
352 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
353 reg-names = "control", "domain";
354 domain-id = <25>;
355 };
356
357 clkvcp5: clkvcp5 {
358 #clock-cells = <0>;
359 compatible = "ti,keystone,psc-clock";
360 clocks = <&chipclk13>;
361 clock-output-names = "vcp-5";
362 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
363 reg-names = "control", "domain";
364 domain-id = <25>;
365 };
366
367 clkvcp6: clkvcp6 {
368 #clock-cells = <0>;
369 compatible = "ti,keystone,psc-clock";
370 clocks = <&chipclk13>;
371 clock-output-names = "vcp-6";
372 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
373 reg-names = "control", "domain";
374 domain-id = <25>;
375 };
376
377 clkvcp7: clkvcp7 {
378 #clock-cells = <0>;
379 compatible = "ti,keystone,psc-clock";
380 clocks = <&chipclk13>;
381 clock-output-names = "vcp-7";
382 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
383 reg-names = "control", "domain";
384 domain-id = <25>;
385 };
386
387 clkbcp: clkbcp {
388 #clock-cells = <0>;
389 compatible = "ti,keystone,psc-clock";
390 clocks = <&chipclk13>;
391 clock-output-names = "bcp";
392 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
393 reg-names = "control", "domain";
394 domain-id = <26>;
395 };
396
397 clkdxb: clkdxb {
398 #clock-cells = <0>;
399 compatible = "ti,keystone,psc-clock";
400 clocks = <&chipclk13>;
401 clock-output-names = "dxb";
402 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
403 reg-names = "control", "domain";
404 domain-id = <27>;
405 };
406
407 clkhyperlink1: clkhyperlink1 {
408 #clock-cells = <0>;
409 compatible = "ti,keystone,psc-clock";
410 clocks = <&chipclk12>;
411 clock-output-names = "hyperlink-1";
412 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
413 reg-names = "control", "domain";
414 domain-id = <28>;
415 };
416
417 clkxge: clkxge {
418 #clock-cells = <0>;
419 compatible = "ti,keystone,psc-clock";
420 clocks = <&chipclk13>;
421 clock-output-names = "xge";
422 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
423 reg-names = "control", "domain";
424 domain-id = <29>;
425 };
426};
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index 1d8ea6e99a7d..d8cc99af51e8 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2013 Texas Instruments, Inc. 2 * Copyright 2013-2014 Texas Instruments, Inc.
3 * 3 *
4 * Keystone 2 Kepler/Hawking EVM device tree 4 * Keystone 2 Kepler/Hawking EVM device tree
5 * 5 *
@@ -10,9 +10,11 @@
10/dts-v1/; 10/dts-v1/;
11 11
12#include "keystone.dtsi" 12#include "keystone.dtsi"
13#include "k2hk.dtsi"
13 14
14/ { 15/ {
15 compatible = "ti,keystone-evm"; 16 compatible = "ti,k2hk-evm";
17 model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
16 18
17 soc { 19 soc {
18 clocks { 20 clocks {
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi
new file mode 100644
index 000000000000..c73899c73118
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk.dtsi
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Kepler/Hawking soc specific device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/ {
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 interrupt-parent = <&gic>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a15";
20 device_type = "cpu";
21 reg = <0>;
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a15";
26 device_type = "cpu";
27 reg = <1>;
28 };
29
30 cpu@2 {
31 compatible = "arm,cortex-a15";
32 device_type = "cpu";
33 reg = <2>;
34 };
35
36 cpu@3 {
37 compatible = "arm,cortex-a15";
38 device_type = "cpu";
39 reg = <3>;
40 };
41 };
42
43 soc {
44 /include/ "k2hk-clocks.dtsi"
45 };
46};
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index a3d1f3d70aad..93f82c7010ab 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -13,51 +13,6 @@ clocks {
13 #size-cells = <1>; 13 #size-cells = <1>;
14 ranges; 14 ranges;
15 15
16 mainpllclk: mainpllclk@2310110 {
17 #clock-cells = <0>;
18 compatible = "ti,keystone,main-pll-clock";
19 clocks = <&refclksys>;
20 reg = <0x02620350 4>, <0x02310110 4>;
21 reg-names = "control", "multiplier";
22 fixed-postdiv = <2>;
23 };
24
25 papllclk: papllclk@2620358 {
26 #clock-cells = <0>;
27 compatible = "ti,keystone,pll-clock";
28 clocks = <&refclkpass>;
29 clock-output-names = "pa-pll-clk";
30 reg = <0x02620358 4>;
31 reg-names = "control";
32 };
33
34 ddr3apllclk: ddr3apllclk@2620360 {
35 #clock-cells = <0>;
36 compatible = "ti,keystone,pll-clock";
37 clocks = <&refclkddr3a>;
38 clock-output-names = "ddr-3a-pll-clk";
39 reg = <0x02620360 4>;
40 reg-names = "control";
41 };
42
43 ddr3bpllclk: ddr3bpllclk@2620368 {
44 #clock-cells = <0>;
45 compatible = "ti,keystone,pll-clock";
46 clocks = <&refclkddr3b>;
47 clock-output-names = "ddr-3b-pll-clk";
48 reg = <0x02620368 4>;
49 reg-names = "control";
50 };
51
52 armpllclk: armpllclk@2620370 {
53 #clock-cells = <0>;
54 compatible = "ti,keystone,pll-clock";
55 clocks = <&refclkarm>;
56 clock-output-names = "arm-pll-clk";
57 reg = <0x02620370 4>;
58 reg-names = "control";
59 };
60
61 mainmuxclk: mainmuxclk@2310108 { 16 mainmuxclk: mainmuxclk@2310108 {
62 #clock-cells = <0>; 17 #clock-cells = <0>;
63 compatible = "ti,keystone,pll-mux-clock"; 18 compatible = "ti,keystone,pll-mux-clock";
@@ -297,26 +252,6 @@ clocks {
297 domain-id = <3>; 252 domain-id = <3>;
298 }; 253 };
299 254
300 clksrio: clksrio {
301 #clock-cells = <0>;
302 compatible = "ti,keystone,psc-clock";
303 clocks = <&chipclk1rstiso13>;
304 clock-output-names = "srio";
305 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
306 reg-names = "control", "domain";
307 domain-id = <4>;
308 };
309
310 clkhyperlink0: clkhyperlink0 {
311 #clock-cells = <0>;
312 compatible = "ti,keystone,psc-clock";
313 clocks = <&chipclk12>;
314 clock-output-names = "hyperlink-0";
315 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
316 reg-names = "control", "domain";
317 domain-id = <5>;
318 };
319
320 clksr: clksr { 255 clksr: clksr {
321 #clock-cells = <0>; 256 #clock-cells = <0>;
322 compatible = "ti,keystone,psc-clock"; 257 compatible = "ti,keystone,psc-clock";
@@ -337,76 +272,6 @@ clocks {
337 domain-id = <8>; 272 domain-id = <8>;
338 }; 273 };
339 274
340 clkgem1: clkgem1 {
341 #clock-cells = <0>;
342 compatible = "ti,keystone,psc-clock";
343 clocks = <&chipclk1>;
344 clock-output-names = "gem1";
345 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
346 reg-names = "control", "domain";
347 domain-id = <9>;
348 };
349
350 clkgem2: clkgem2 {
351 #clock-cells = <0>;
352 compatible = "ti,keystone,psc-clock";
353 clocks = <&chipclk1>;
354 clock-output-names = "gem2";
355 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
356 reg-names = "control", "domain";
357 domain-id = <10>;
358 };
359
360 clkgem3: clkgem3 {
361 #clock-cells = <0>;
362 compatible = "ti,keystone,psc-clock";
363 clocks = <&chipclk1>;
364 clock-output-names = "gem3";
365 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
366 reg-names = "control", "domain";
367 domain-id = <11>;
368 };
369
370 clkgem4: clkgem4 {
371 #clock-cells = <0>;
372 compatible = "ti,keystone,psc-clock";
373 clocks = <&chipclk1>;
374 clock-output-names = "gem4";
375 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
376 reg-names = "control", "domain";
377 domain-id = <12>;
378 };
379
380 clkgem5: clkgem5 {
381 #clock-cells = <0>;
382 compatible = "ti,keystone,psc-clock";
383 clocks = <&chipclk1>;
384 clock-output-names = "gem5";
385 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
386 reg-names = "control", "domain";
387 domain-id = <13>;
388 };
389
390 clkgem6: clkgem6 {
391 #clock-cells = <0>;
392 compatible = "ti,keystone,psc-clock";
393 clocks = <&chipclk1>;
394 clock-output-names = "gem6";
395 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
396 reg-names = "control", "domain";
397 domain-id = <14>;
398 };
399
400 clkgem7: clkgem7 {
401 #clock-cells = <0>;
402 compatible = "ti,keystone,psc-clock";
403 clocks = <&chipclk1>;
404 clock-output-names = "gem7";
405 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
406 reg-names = "control", "domain";
407 domain-id = <15>;
408 };
409
410 clkddr30: clkddr30 { 275 clkddr30: clkddr30 {
411 #clock-cells = <0>; 276 #clock-cells = <0>;
412 compatible = "ti,keystone,psc-clock"; 277 compatible = "ti,keystone,psc-clock";
@@ -417,276 +282,6 @@ clocks {
417 domain-id = <16>; 282 domain-id = <16>;
418 }; 283 };
419 284
420 clkddr31: clkddr31 {
421 #clock-cells = <0>;
422 compatible = "ti,keystone,psc-clock";
423 clocks = <&chipclk13>;
424 clock-output-names = "ddr3-1";
425 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
426 reg-names = "control", "domain";
427 domain-id = <16>;
428 };
429
430 clktac: clktac {
431 #clock-cells = <0>;
432 compatible = "ti,keystone,psc-clock";
433 clocks = <&chipclk13>;
434 clock-output-names = "tac";
435 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
436 reg-names = "control", "domain";
437 domain-id = <17>;
438 };
439
440 clkrac01: clktac01 {
441 #clock-cells = <0>;
442 compatible = "ti,keystone,psc-clock";
443 clocks = <&chipclk13>;
444 clock-output-names = "rac-01";
445 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
446 reg-names = "control", "domain";
447 domain-id = <17>;
448 };
449
450 clkrac23: clktac23 {
451 #clock-cells = <0>;
452 compatible = "ti,keystone,psc-clock";
453 clocks = <&chipclk13>;
454 clock-output-names = "rac-23";
455 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
456 reg-names = "control", "domain";
457 domain-id = <18>;
458 };
459
460 clkfftc0: clkfftc0 {
461 #clock-cells = <0>;
462 compatible = "ti,keystone,psc-clock";
463 clocks = <&chipclk13>;
464 clock-output-names = "fftc-0";
465 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
466 reg-names = "control", "domain";
467 domain-id = <19>;
468 };
469
470 clkfftc1: clkfftc1 {
471 #clock-cells = <0>;
472 compatible = "ti,keystone,psc-clock";
473 clocks = <&chipclk13>;
474 clock-output-names = "fftc-1";
475 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
476 reg-names = "control", "domain";
477 domain-id = <19>;
478 };
479
480 clkfftc2: clkfftc2 {
481 #clock-cells = <0>;
482 compatible = "ti,keystone,psc-clock";
483 clocks = <&chipclk13>;
484 clock-output-names = "fftc-2";
485 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
486 reg-names = "control", "domain";
487 domain-id = <20>;
488 };
489
490 clkfftc3: clkfftc3 {
491 #clock-cells = <0>;
492 compatible = "ti,keystone,psc-clock";
493 clocks = <&chipclk13>;
494 clock-output-names = "fftc-3";
495 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
496 reg-names = "control", "domain";
497 domain-id = <20>;
498 };
499
500 clkfftc4: clkfftc4 {
501 #clock-cells = <0>;
502 compatible = "ti,keystone,psc-clock";
503 clocks = <&chipclk13>;
504 clock-output-names = "fftc-4";
505 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
506 reg-names = "control", "domain";
507 domain-id = <20>;
508 };
509
510 clkfftc5: clkfftc5 {
511 #clock-cells = <0>;
512 compatible = "ti,keystone,psc-clock";
513 clocks = <&chipclk13>;
514 clock-output-names = "fftc-5";
515 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
516 reg-names = "control", "domain";
517 domain-id = <20>;
518 };
519
520 clkaif: clkaif {
521 #clock-cells = <0>;
522 compatible = "ti,keystone,psc-clock";
523 clocks = <&chipclk13>;
524 clock-output-names = "aif";
525 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
526 reg-names = "control", "domain";
527 domain-id = <21>;
528 };
529
530 clktcp3d0: clktcp3d0 {
531 #clock-cells = <0>;
532 compatible = "ti,keystone,psc-clock";
533 clocks = <&chipclk13>;
534 clock-output-names = "tcp3d-0";
535 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
536 reg-names = "control", "domain";
537 domain-id = <22>;
538 };
539
540 clktcp3d1: clktcp3d1 {
541 #clock-cells = <0>;
542 compatible = "ti,keystone,psc-clock";
543 clocks = <&chipclk13>;
544 clock-output-names = "tcp3d-1";
545 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
546 reg-names = "control", "domain";
547 domain-id = <22>;
548 };
549
550 clktcp3d2: clktcp3d2 {
551 #clock-cells = <0>;
552 compatible = "ti,keystone,psc-clock";
553 clocks = <&chipclk13>;
554 clock-output-names = "tcp3d-2";
555 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
556 reg-names = "control", "domain";
557 domain-id = <23>;
558 };
559
560 clktcp3d3: clktcp3d3 {
561 #clock-cells = <0>;
562 compatible = "ti,keystone,psc-clock";
563 clocks = <&chipclk13>;
564 clock-output-names = "tcp3d-3";
565 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
566 reg-names = "control", "domain";
567 domain-id = <23>;
568 };
569
570 clkvcp0: clkvcp0 {
571 #clock-cells = <0>;
572 compatible = "ti,keystone,psc-clock";
573 clocks = <&chipclk13>;
574 clock-output-names = "vcp-0";
575 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
576 reg-names = "control", "domain";
577 domain-id = <24>;
578 };
579
580 clkvcp1: clkvcp1 {
581 #clock-cells = <0>;
582 compatible = "ti,keystone,psc-clock";
583 clocks = <&chipclk13>;
584 clock-output-names = "vcp-1";
585 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
586 reg-names = "control", "domain";
587 domain-id = <24>;
588 };
589
590 clkvcp2: clkvcp2 {
591 #clock-cells = <0>;
592 compatible = "ti,keystone,psc-clock";
593 clocks = <&chipclk13>;
594 clock-output-names = "vcp-2";
595 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
596 reg-names = "control", "domain";
597 domain-id = <24>;
598 };
599
600 clkvcp3: clkvcp3 {
601 #clock-cells = <0>;
602 compatible = "ti,keystone,psc-clock";
603 clocks = <&chipclk13>;
604 clock-output-names = "vcp-3";
605 reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
606 reg-names = "control", "domain";
607 domain-id = <24>;
608 };
609
610 clkvcp4: clkvcp4 {
611 #clock-cells = <0>;
612 compatible = "ti,keystone,psc-clock";
613 clocks = <&chipclk13>;
614 clock-output-names = "vcp-4";
615 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
616 reg-names = "control", "domain";
617 domain-id = <25>;
618 };
619
620 clkvcp5: clkvcp5 {
621 #clock-cells = <0>;
622 compatible = "ti,keystone,psc-clock";
623 clocks = <&chipclk13>;
624 clock-output-names = "vcp-5";
625 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
626 reg-names = "control", "domain";
627 domain-id = <25>;
628 };
629
630 clkvcp6: clkvcp6 {
631 #clock-cells = <0>;
632 compatible = "ti,keystone,psc-clock";
633 clocks = <&chipclk13>;
634 clock-output-names = "vcp-6";
635 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
636 reg-names = "control", "domain";
637 domain-id = <25>;
638 };
639
640 clkvcp7: clkvcp7 {
641 #clock-cells = <0>;
642 compatible = "ti,keystone,psc-clock";
643 clocks = <&chipclk13>;
644 clock-output-names = "vcp-7";
645 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
646 reg-names = "control", "domain";
647 domain-id = <25>;
648 };
649
650 clkbcp: clkbcp {
651 #clock-cells = <0>;
652 compatible = "ti,keystone,psc-clock";
653 clocks = <&chipclk13>;
654 clock-output-names = "bcp";
655 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
656 reg-names = "control", "domain";
657 domain-id = <26>;
658 };
659
660 clkdxb: clkdxb {
661 #clock-cells = <0>;
662 compatible = "ti,keystone,psc-clock";
663 clocks = <&chipclk13>;
664 clock-output-names = "dxb";
665 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
666 reg-names = "control", "domain";
667 domain-id = <27>;
668 };
669
670 clkhyperlink1: clkhyperlink1 {
671 #clock-cells = <0>;
672 compatible = "ti,keystone,psc-clock";
673 clocks = <&chipclk12>;
674 clock-output-names = "hyperlink-1";
675 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
676 reg-names = "control", "domain";
677 domain-id = <28>;
678 };
679
680 clkxge: clkxge {
681 #clock-cells = <0>;
682 compatible = "ti,keystone,psc-clock";
683 clocks = <&chipclk13>;
684 clock-output-names = "xge";
685 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
686 reg-names = "control", "domain";
687 domain-id = <29>;
688 };
689
690 clkwdtimer0: clkwdtimer0 { 285 clkwdtimer0: clkwdtimer0 {
691 #clock-cells = <0>; 286 #clock-cells = <0>;
692 compatible = "ti,keystone,psc-clock"; 287 compatible = "ti,keystone,psc-clock";
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 4eceb464ff0b..1992351e09fa 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -25,37 +25,6 @@
25 reg = <0x00000000 0x80000000 0x00000000 0x40000000>; 25 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
26 }; 26 };
27 27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 interrupt-parent = <&gic>;
33
34 cpu@0 {
35 compatible = "arm,cortex-a15";
36 device_type = "cpu";
37 reg = <0>;
38 };
39
40 cpu@1 {
41 compatible = "arm,cortex-a15";
42 device_type = "cpu";
43 reg = <1>;
44 };
45
46 cpu@2 {
47 compatible = "arm,cortex-a15";
48 device_type = "cpu";
49 reg = <2>;
50 };
51
52 cpu@3 {
53 compatible = "arm,cortex-a15";
54 device_type = "cpu";
55 reg = <3>;
56 };
57 };
58
59 gic: interrupt-controller { 28 gic: interrupt-controller {
60 compatible = "arm,cortex-a15-gic"; 29 compatible = "arm,cortex-a15-gic";
61 #interrupt-cells = <3>; 30 #interrupt-cells = <3>;