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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-27 19:47:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-27 19:47:35 -0400
commit66f03c614c0902ccf7d6160459362a9352f33271 (patch)
treeb9a8864efe5aa7fc5c96cc5ccbeca41f5cd6f6a7 /arch/arm/boot/dts
parent34800598b2eebe061445216473b1e4c2ff5cba99 (diff)
parentcdc3df6f44f72c5924a16a47e1663c3fb0e57820 (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: device tree work" from Arnd Bergmann: "Most of these patches convert code from using static platform data to describing the hardware in the device tree. This is only the first half of the changes for v3.4 because a lot of patches for this topic came in the last week before the merge window. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up trivial conflicts in arch/arm/mach-vexpress/{Kconfig,core.h} * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (86 commits) Document: devicetree: add OF documents for arch-mmp ARM: dts: append DTS file of pxa168 ARM: mmp: append OF support on pxa168 ARM: mmp: enable rtc clk in pxa168 i2c: pxa: add OF support serial: pxa: add OF support arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board ARM: OMAP2+: Remove extra ifdefs for board-generic ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected ASoC: DT: Add digital microphone binding to PAZ00 board. ARM: dt: Add ARM PMU to tegra*.dtsi ARM: at91: at91sam9x5cm/dt: add leds support ARM: at91: usb_a9g20/dt: add gpio-keys support ARM: at91: at91sam9m10g45ek/dt: add gpio-keys support ARM: at91: at91sam9m10g45ek/dt: add leds support ARM: at91: usb_a9g20/dt: add leds support ARM: at91/pio: add new PIO3 features ARM: at91: add sam9_smc.o to at91sam9x5 build ARM: at91/tc/clocksource: Add 32 bit variant to Timer Counter ARM: at91/tc: add device tree support to atmel_tclib ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/am3517_mt_ventoux.dts27
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi68
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi87
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts72
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9x5cm.dtsi15
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts76
-rw-r--r--arch/arm/boot/dts/imx27.dtsi217
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts91
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts34
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts9
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts20
-rw-r--r--arch/arm/boot/dts/omap3.dtsi35
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts9
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts9
-rw-r--r--arch/arm/boot/dts/omap4.dtsi38
-rw-r--r--arch/arm/boot/dts/pxa168-aspenite.dts38
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi98
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts18
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts3
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi8
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts23
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi201
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi200
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts157
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts162
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts192
29 files changed, 1877 insertions, 62 deletions
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
new file mode 100644
index 000000000000..5eb26d7d9b4e
--- /dev/null
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TeeJet Mt.Ventoux";
14 compatible = "teejet,mt_ventoux", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 /* AM35xx doesn't have IVA */
22 soc {
23 iva {
24 status = "disabled";
25 };
26 };
27};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 07603b8c9503..a100db03ec90 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -23,6 +23,11 @@
23 serial4 = &usart3; 23 serial4 = &usart3;
24 serial5 = &usart4; 24 serial5 = &usart4;
25 serial6 = &usart5; 25 serial6 = &usart5;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
26 }; 31 };
27 cpus { 32 cpus {
28 cpu@0 { 33 cpu@0 {
@@ -47,24 +52,69 @@
47 ranges; 52 ranges;
48 53
49 aic: interrupt-controller@fffff000 { 54 aic: interrupt-controller@fffff000 {
50 #interrupt-cells = <1>; 55 #interrupt-cells = <2>;
51 compatible = "atmel,at91rm9200-aic"; 56 compatible = "atmel,at91rm9200-aic";
52 interrupt-controller; 57 interrupt-controller;
53 interrupt-parent; 58 interrupt-parent;
54 reg = <0xfffff000 0x200>; 59 reg = <0xfffff000 0x200>;
55 }; 60 };
56 61
62 pit: timer@fffffd30 {
63 compatible = "atmel,at91sam9260-pit";
64 reg = <0xfffffd30 0xf>;
65 interrupts = <1 4>;
66 };
67
68 tcb0: timer@fffa0000 {
69 compatible = "atmel,at91rm9200-tcb";
70 reg = <0xfffa0000 0x100>;
71 interrupts = <17 4 18 4 19 4>;
72 };
73
74 tcb1: timer@fffdc000 {
75 compatible = "atmel,at91rm9200-tcb";
76 reg = <0xfffdc000 0x100>;
77 interrupts = <26 4 27 4 28 4>;
78 };
79
80 pioA: gpio@fffff400 {
81 compatible = "atmel,at91rm9200-gpio";
82 reg = <0xfffff400 0x100>;
83 interrupts = <2 4>;
84 #gpio-cells = <2>;
85 gpio-controller;
86 interrupt-controller;
87 };
88
89 pioB: gpio@fffff600 {
90 compatible = "atmel,at91rm9200-gpio";
91 reg = <0xfffff600 0x100>;
92 interrupts = <3 4>;
93 #gpio-cells = <2>;
94 gpio-controller;
95 interrupt-controller;
96 };
97
98 pioC: gpio@fffff800 {
99 compatible = "atmel,at91rm9200-gpio";
100 reg = <0xfffff800 0x100>;
101 interrupts = <4 4>;
102 #gpio-cells = <2>;
103 gpio-controller;
104 interrupt-controller;
105 };
106
57 dbgu: serial@fffff200 { 107 dbgu: serial@fffff200 {
58 compatible = "atmel,at91sam9260-usart"; 108 compatible = "atmel,at91sam9260-usart";
59 reg = <0xfffff200 0x200>; 109 reg = <0xfffff200 0x200>;
60 interrupts = <1>; 110 interrupts = <1 4>;
61 status = "disabled"; 111 status = "disabled";
62 }; 112 };
63 113
64 usart0: serial@fffb0000 { 114 usart0: serial@fffb0000 {
65 compatible = "atmel,at91sam9260-usart"; 115 compatible = "atmel,at91sam9260-usart";
66 reg = <0xfffb0000 0x200>; 116 reg = <0xfffb0000 0x200>;
67 interrupts = <6>; 117 interrupts = <6 4>;
68 atmel,use-dma-rx; 118 atmel,use-dma-rx;
69 atmel,use-dma-tx; 119 atmel,use-dma-tx;
70 status = "disabled"; 120 status = "disabled";
@@ -73,7 +123,7 @@
73 usart1: serial@fffb4000 { 123 usart1: serial@fffb4000 {
74 compatible = "atmel,at91sam9260-usart"; 124 compatible = "atmel,at91sam9260-usart";
75 reg = <0xfffb4000 0x200>; 125 reg = <0xfffb4000 0x200>;
76 interrupts = <7>; 126 interrupts = <7 4>;
77 atmel,use-dma-rx; 127 atmel,use-dma-rx;
78 atmel,use-dma-tx; 128 atmel,use-dma-tx;
79 status = "disabled"; 129 status = "disabled";
@@ -82,7 +132,7 @@
82 usart2: serial@fffb8000 { 132 usart2: serial@fffb8000 {
83 compatible = "atmel,at91sam9260-usart"; 133 compatible = "atmel,at91sam9260-usart";
84 reg = <0xfffb8000 0x200>; 134 reg = <0xfffb8000 0x200>;
85 interrupts = <8>; 135 interrupts = <8 4>;
86 atmel,use-dma-rx; 136 atmel,use-dma-rx;
87 atmel,use-dma-tx; 137 atmel,use-dma-tx;
88 status = "disabled"; 138 status = "disabled";
@@ -91,7 +141,7 @@
91 usart3: serial@fffd0000 { 141 usart3: serial@fffd0000 {
92 compatible = "atmel,at91sam9260-usart"; 142 compatible = "atmel,at91sam9260-usart";
93 reg = <0xfffd0000 0x200>; 143 reg = <0xfffd0000 0x200>;
94 interrupts = <23>; 144 interrupts = <23 4>;
95 atmel,use-dma-rx; 145 atmel,use-dma-rx;
96 atmel,use-dma-tx; 146 atmel,use-dma-tx;
97 status = "disabled"; 147 status = "disabled";
@@ -100,7 +150,7 @@
100 usart4: serial@fffd4000 { 150 usart4: serial@fffd4000 {
101 compatible = "atmel,at91sam9260-usart"; 151 compatible = "atmel,at91sam9260-usart";
102 reg = <0xfffd4000 0x200>; 152 reg = <0xfffd4000 0x200>;
103 interrupts = <24>; 153 interrupts = <24 4>;
104 atmel,use-dma-rx; 154 atmel,use-dma-rx;
105 atmel,use-dma-tx; 155 atmel,use-dma-tx;
106 status = "disabled"; 156 status = "disabled";
@@ -109,7 +159,7 @@
109 usart5: serial@fffd8000 { 159 usart5: serial@fffd8000 {
110 compatible = "atmel,at91sam9260-usart"; 160 compatible = "atmel,at91sam9260-usart";
111 reg = <0xfffd8000 0x200>; 161 reg = <0xfffd8000 0x200>;
112 interrupts = <25>; 162 interrupts = <25 4>;
113 atmel,use-dma-rx; 163 atmel,use-dma-rx;
114 atmel,use-dma-tx; 164 atmel,use-dma-tx;
115 status = "disabled"; 165 status = "disabled";
@@ -118,7 +168,7 @@
118 macb0: ethernet@fffc4000 { 168 macb0: ethernet@fffc4000 {
119 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 169 compatible = "cdns,at32ap7000-macb", "cdns,macb";
120 reg = <0xfffc4000 0x100>; 170 reg = <0xfffc4000 0x100>;
121 interrupts = <21>; 171 interrupts = <21 4>;
122 status = "disabled"; 172 status = "disabled";
123 }; 173 };
124 }; 174 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index fffa005300a4..f779667159b1 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -22,6 +22,13 @@
22 serial2 = &usart1; 22 serial2 = &usart1;
23 serial3 = &usart2; 23 serial3 = &usart2;
24 serial4 = &usart3; 24 serial4 = &usart3;
25 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
25 }; 32 };
26 cpus { 33 cpus {
27 cpu@0 { 34 cpu@0 {
@@ -46,30 +53,94 @@
46 ranges; 53 ranges;
47 54
48 aic: interrupt-controller@fffff000 { 55 aic: interrupt-controller@fffff000 {
49 #interrupt-cells = <1>; 56 #interrupt-cells = <2>;
50 compatible = "atmel,at91rm9200-aic"; 57 compatible = "atmel,at91rm9200-aic";
51 interrupt-controller; 58 interrupt-controller;
52 interrupt-parent; 59 interrupt-parent;
53 reg = <0xfffff000 0x200>; 60 reg = <0xfffff000 0x200>;
54 }; 61 };
55 62
63 pit: timer@fffffd30 {
64 compatible = "atmel,at91sam9260-pit";
65 reg = <0xfffffd30 0xf>;
66 interrupts = <1 4>;
67 };
68
69
70 tcb0: timer@fff7c000 {
71 compatible = "atmel,at91rm9200-tcb";
72 reg = <0xfff7c000 0x100>;
73 interrupts = <18 4>;
74 };
75
76 tcb1: timer@fffd4000 {
77 compatible = "atmel,at91rm9200-tcb";
78 reg = <0xfffd4000 0x100>;
79 interrupts = <18 4>;
80 };
81
56 dma: dma-controller@ffffec00 { 82 dma: dma-controller@ffffec00 {
57 compatible = "atmel,at91sam9g45-dma"; 83 compatible = "atmel,at91sam9g45-dma";
58 reg = <0xffffec00 0x200>; 84 reg = <0xffffec00 0x200>;
59 interrupts = <21>; 85 interrupts = <21 4>;
86 };
87
88 pioA: gpio@fffff200 {
89 compatible = "atmel,at91rm9200-gpio";
90 reg = <0xfffff200 0x100>;
91 interrupts = <2 4>;
92 #gpio-cells = <2>;
93 gpio-controller;
94 interrupt-controller;
95 };
96
97 pioB: gpio@fffff400 {
98 compatible = "atmel,at91rm9200-gpio";
99 reg = <0xfffff400 0x100>;
100 interrupts = <3 4>;
101 #gpio-cells = <2>;
102 gpio-controller;
103 interrupt-controller;
104 };
105
106 pioC: gpio@fffff600 {
107 compatible = "atmel,at91rm9200-gpio";
108 reg = <0xfffff600 0x100>;
109 interrupts = <4 4>;
110 #gpio-cells = <2>;
111 gpio-controller;
112 interrupt-controller;
113 };
114
115 pioD: gpio@fffff800 {
116 compatible = "atmel,at91rm9200-gpio";
117 reg = <0xfffff800 0x100>;
118 interrupts = <5 4>;
119 #gpio-cells = <2>;
120 gpio-controller;
121 interrupt-controller;
122 };
123
124 pioE: gpio@fffffa00 {
125 compatible = "atmel,at91rm9200-gpio";
126 reg = <0xfffffa00 0x100>;
127 interrupts = <5 4>;
128 #gpio-cells = <2>;
129 gpio-controller;
130 interrupt-controller;
60 }; 131 };
61 132
62 dbgu: serial@ffffee00 { 133 dbgu: serial@ffffee00 {
63 compatible = "atmel,at91sam9260-usart"; 134 compatible = "atmel,at91sam9260-usart";
64 reg = <0xffffee00 0x200>; 135 reg = <0xffffee00 0x200>;
65 interrupts = <1>; 136 interrupts = <1 4>;
66 status = "disabled"; 137 status = "disabled";
67 }; 138 };
68 139
69 usart0: serial@fff8c000 { 140 usart0: serial@fff8c000 {
70 compatible = "atmel,at91sam9260-usart"; 141 compatible = "atmel,at91sam9260-usart";
71 reg = <0xfff8c000 0x200>; 142 reg = <0xfff8c000 0x200>;
72 interrupts = <7>; 143 interrupts = <7 4>;
73 atmel,use-dma-rx; 144 atmel,use-dma-rx;
74 atmel,use-dma-tx; 145 atmel,use-dma-tx;
75 status = "disabled"; 146 status = "disabled";
@@ -78,7 +149,7 @@
78 usart1: serial@fff90000 { 149 usart1: serial@fff90000 {
79 compatible = "atmel,at91sam9260-usart"; 150 compatible = "atmel,at91sam9260-usart";
80 reg = <0xfff90000 0x200>; 151 reg = <0xfff90000 0x200>;
81 interrupts = <8>; 152 interrupts = <8 4>;
82 atmel,use-dma-rx; 153 atmel,use-dma-rx;
83 atmel,use-dma-tx; 154 atmel,use-dma-tx;
84 status = "disabled"; 155 status = "disabled";
@@ -87,7 +158,7 @@
87 usart2: serial@fff94000 { 158 usart2: serial@fff94000 {
88 compatible = "atmel,at91sam9260-usart"; 159 compatible = "atmel,at91sam9260-usart";
89 reg = <0xfff94000 0x200>; 160 reg = <0xfff94000 0x200>;
90 interrupts = <9>; 161 interrupts = <9 4>;
91 atmel,use-dma-rx; 162 atmel,use-dma-rx;
92 atmel,use-dma-tx; 163 atmel,use-dma-tx;
93 status = "disabled"; 164 status = "disabled";
@@ -96,7 +167,7 @@
96 usart3: serial@fff98000 { 167 usart3: serial@fff98000 {
97 compatible = "atmel,at91sam9260-usart"; 168 compatible = "atmel,at91sam9260-usart";
98 reg = <0xfff98000 0x200>; 169 reg = <0xfff98000 0x200>;
99 interrupts = <10>; 170 interrupts = <10 4>;
100 atmel,use-dma-rx; 171 atmel,use-dma-rx;
101 atmel,use-dma-tx; 172 atmel,use-dma-tx;
102 status = "disabled"; 173 status = "disabled";
@@ -105,7 +176,7 @@
105 macb0: ethernet@fffbc000 { 176 macb0: ethernet@fffbc000 {
106 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 177 compatible = "cdns,at32ap7000-macb", "cdns,macb";
107 reg = <0xfffbc000 0x100>; 178 reg = <0xfffbc000 0x100>;
108 interrupts = <25>; 179 interrupts = <25 4>;
109 status = "disabled"; 180 status = "disabled";
110 }; 181 };
111 }; 182 };
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a387e7704ce1..15e25f903cad 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -37,4 +37,76 @@
37 }; 37 };
38 }; 38 };
39 }; 39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 d8 {
45 label = "d8";
46 gpios = <&pioD 30 0>;
47 linux,default-trigger = "heartbeat";
48 };
49
50 d6 {
51 label = "d6";
52 gpios = <&pioD 0 1>;
53 linux,default-trigger = "nand-disk";
54 };
55
56 d7 {
57 label = "d7";
58 gpios = <&pioD 31 1>;
59 linux,default-trigger = "mmc0";
60 };
61 };
62
63 gpio_keys {
64 compatible = "gpio-keys";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 left_click {
69 label = "left_click";
70 gpios = <&pioB 6 1>;
71 linux,code = <272>;
72 gpio-key,wakeup;
73 };
74
75 right_click {
76 label = "right_click";
77 gpios = <&pioB 7 1>;
78 linux,code = <273>;
79 gpio-key,wakeup;
80 };
81
82 left {
83 label = "Joystick Left";
84 gpios = <&pioB 14 1>;
85 linux,code = <105>;
86 };
87
88 right {
89 label = "Joystick Right";
90 gpios = <&pioB 15 1>;
91 linux,code = <106>;
92 };
93
94 up {
95 label = "Joystick Up";
96 gpios = <&pioB 16 1>;
97 linux,code = <103>;
98 };
99
100 down {
101 label = "Joystick Down";
102 gpios = <&pioB 17 1>;
103 linux,code = <108>;
104 };
105
106 enter {
107 label = "Joystick Press";
108 gpios = <&pioB 18 1>;
109 linux,code = <28>;
110 };
111 };
40}; 112};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e91391f50730..a02e636d8a57 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -89,35 +89,39 @@
89 }; 89 };
90 90
91 pioA: gpio@fffff400 { 91 pioA: gpio@fffff400 {
92 compatible = "atmel,at91rm9200-gpio"; 92 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
93 reg = <0xfffff400 0x100>; 93 reg = <0xfffff400 0x100>;
94 interrupts = <2 4>; 94 interrupts = <2 4>;
95 #gpio-cells = <2>; 95 #gpio-cells = <2>;
96 gpio-controller; 96 gpio-controller;
97 interrupt-controller;
97 }; 98 };
98 99
99 pioB: gpio@fffff600 { 100 pioB: gpio@fffff600 {
100 compatible = "atmel,at91rm9200-gpio"; 101 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
101 reg = <0xfffff600 0x100>; 102 reg = <0xfffff600 0x100>;
102 interrupts = <2 4>; 103 interrupts = <2 4>;
103 #gpio-cells = <2>; 104 #gpio-cells = <2>;
104 gpio-controller; 105 gpio-controller;
106 interrupt-controller;
105 }; 107 };
106 108
107 pioC: gpio@fffff800 { 109 pioC: gpio@fffff800 {
108 compatible = "atmel,at91rm9200-gpio"; 110 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
109 reg = <0xfffff800 0x100>; 111 reg = <0xfffff800 0x100>;
110 interrupts = <3 4>; 112 interrupts = <3 4>;
111 #gpio-cells = <2>; 113 #gpio-cells = <2>;
112 gpio-controller; 114 gpio-controller;
115 interrupt-controller;
113 }; 116 };
114 117
115 pioD: gpio@fffffa00 { 118 pioD: gpio@fffffa00 {
116 compatible = "atmel,at91rm9200-gpio"; 119 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
117 reg = <0xfffffa00 0x100>; 120 reg = <0xfffffa00 0x100>;
118 interrupts = <3 4>; 121 interrupts = <3 4>;
119 #gpio-cells = <2>; 122 #gpio-cells = <2>;
120 gpio-controller; 123 gpio-controller;
124 interrupt-controller;
121 }; 125 };
122 126
123 dbgu: serial@fffff200 { 127 dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4ab5a77f4afc..64ae3e890259 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -11,4 +11,19 @@
11 memory@20000000 { 11 memory@20000000 {
12 reg = <0x20000000 0x8000000>; 12 reg = <0x20000000 0x8000000>;
13 }; 13 };
14
15 leds {
16 compatible = "gpio-leds";
17
18 pb18 {
19 label = "pb18";
20 gpios = <&pioB 18 1>;
21 linux,default-trigger = "heartbeat";
22 };
23
24 pd21 {
25 label = "pd21";
26 gpios = <&pioD 21 0>;
27 };
28 };
14}; 29};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
new file mode 100644
index 000000000000..a51a08fc2af9
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx27.dtsi"
14
15/ {
16 model = "Phytec pcm038";
17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18
19 memory {
20 reg = <0x0 0x0>;
21 };
22
23 soc {
24 aipi@10000000 { /* aipi */
25
26 wdog@10002000 {
27 status = "okay";
28 };
29
30 uart@1000a000 {
31 fsl,uart-has-rtscts;
32 status = "okay";
33 };
34
35 uart@1000b000 {
36 fsl,uart-has-rtscts;
37 status = "okay";
38 };
39
40 uart@1000c000 {
41 fsl,uart-has-rtscts;
42 status = "okay";
43 };
44
45 fec@1002b000 {
46 status = "okay";
47 };
48
49 i2c@1001d000 {
50 clock-frequency = <400000>;
51 status = "okay";
52 at24@4c {
53 compatible = "at,24c32";
54 pagesize = <32>;
55 reg = <0x52>;
56 };
57 pcf8563@51 {
58 compatible = "nxp,pcf8563";
59 reg = <0x51>;
60 };
61 lm75@4a {
62 compatible = "national,lm75";
63 reg = <0x4a>;
64 };
65 };
66 };
67 };
68
69 nor_flash@c0000000 {
70 compatible = "cfi-flash";
71 bank-width = <2>;
72 reg = <0xc0000000 0x02000000>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 };
76};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
new file mode 100644
index 000000000000..bc5e7d5ddd54
--- /dev/null
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -0,0 +1,217 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 serial5 = &uart6;
22 };
23
24 avic: avic-interrupt-controller@e0000000 {
25 compatible = "fsl,imx27-avic", "fsl,avic";
26 interrupt-controller;
27 #interrupt-cells = <1>;
28 reg = <0x10040000 0x1000>;
29 };
30
31 clocks {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 osc26m {
36 compatible = "fsl,imx-osc26m", "fixed-clock";
37 clock-frequency = <26000000>;
38 };
39 };
40
41 soc {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "simple-bus";
45 interrupt-parent = <&avic>;
46 ranges;
47
48 aipi@10000000 { /* AIPI1 */
49 compatible = "fsl,aipi-bus", "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 reg = <0x10000000 0x10000000>;
53 ranges;
54
55 wdog@10002000 {
56 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
57 reg = <0x10002000 0x4000>;
58 interrupts = <27>;
59 status = "disabled";
60 };
61
62 uart1: uart@1000a000 {
63 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
64 reg = <0x1000a000 0x1000>;
65 interrupts = <20>;
66 status = "disabled";
67 };
68
69 uart2: uart@1000b000 {
70 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
71 reg = <0x1000b000 0x1000>;
72 interrupts = <19>;
73 status = "disabled";
74 };
75
76 uart3: uart@1000c000 {
77 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
78 reg = <0x1000c000 0x1000>;
79 interrupts = <18>;
80 status = "disabled";
81 };
82
83 uart4: uart@1000d000 {
84 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
85 reg = <0x1000d000 0x1000>;
86 interrupts = <17>;
87 status = "disabled";
88 };
89
90 cspi1: cspi@1000e000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "fsl,imx27-cspi";
94 reg = <0x1000e000 0x1000>;
95 interrupts = <16>;
96 status = "disabled";
97 };
98
99 cspi2: cspi@1000f000 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 compatible = "fsl,imx27-cspi";
103 reg = <0x1000f000 0x1000>;
104 interrupts = <15>;
105 status = "disabled";
106 };
107
108 i2c1: i2c@10012000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
112 reg = <0x10012000 0x1000>;
113 interrupts = <12>;
114 status = "disabled";
115 };
116
117 gpio1: gpio@10015000 {
118 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
119 reg = <0x10015000 0x100>;
120 interrupts = <8>;
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <1>;
125 };
126
127 gpio2: gpio@10015100 {
128 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
129 reg = <0x10015100 0x100>;
130 interrupts = <8>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <1>;
135 };
136
137 gpio3: gpio@10015200 {
138 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
139 reg = <0x10015200 0x100>;
140 interrupts = <8>;
141 gpio-controller;
142 #gpio-cells = <2>;
143 interrupt-controller;
144 #interrupt-cells = <1>;
145 };
146
147 gpio4: gpio@10015300 {
148 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
149 reg = <0x10015300 0x100>;
150 interrupts = <8>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
154 #interrupt-cells = <1>;
155 };
156
157 gpio5: gpio@10015400 {
158 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
159 reg = <0x10015400 0x100>;
160 interrupts = <8>;
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
165 };
166
167 gpio6: gpio@10015500 {
168 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
169 reg = <0x10015500 0x100>;
170 interrupts = <8>;
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <1>;
175 };
176
177 cspi3: cspi@10017000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx27-cspi";
181 reg = <0x10017000 0x1000>;
182 interrupts = <6>;
183 status = "disabled";
184 };
185
186 uart5: uart@1001b000 {
187 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
188 reg = <0x1001b000 0x1000>;
189 interrupts = <49>;
190 status = "disabled";
191 };
192
193 uart6: uart@1001c000 {
194 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
195 reg = <0x1001c000 0x1000>;
196 interrupts = <48>;
197 status = "disabled";
198 };
199
200 i2c2: i2c@1001d000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
204 reg = <0x1001d000 0x1000>;
205 interrupts = <1>;
206 status = "disabled";
207 };
208
209 fec: fec@1002b000 {
210 compatible = "fsl,imx27-fec";
211 reg = <0x1002b000 0x4000>;
212 interrupts = <50>;
213 status = "disabled";
214 };
215 };
216 };
217};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 564cb8c19f15..9949e6060dee 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -56,8 +56,95 @@
56 compatible = "fsl,mc13892"; 56 compatible = "fsl,mc13892";
57 spi-max-frequency = <6000000>; 57 spi-max-frequency = <6000000>;
58 reg = <0>; 58 reg = <0>;
59 mc13xxx-irq-gpios = <&gpio1 8 0>; 59 interrupt-parent = <&gpio1>;
60 fsl,mc13xxx-uses-regulator; 60 interrupts = <8>;
61
62 regulators {
63 sw1_reg: sw1 {
64 regulator-min-microvolt = <600000>;
65 regulator-max-microvolt = <1375000>;
66 regulator-boot-on;
67 regulator-always-on;
68 };
69
70 sw2_reg: sw2 {
71 regulator-min-microvolt = <900000>;
72 regulator-max-microvolt = <1850000>;
73 regulator-boot-on;
74 regulator-always-on;
75 };
76
77 sw3_reg: sw3 {
78 regulator-min-microvolt = <1100000>;
79 regulator-max-microvolt = <1850000>;
80 regulator-boot-on;
81 regulator-always-on;
82 };
83
84 sw4_reg: sw4 {
85 regulator-min-microvolt = <1100000>;
86 regulator-max-microvolt = <1850000>;
87 regulator-boot-on;
88 regulator-always-on;
89 };
90
91 vpll_reg: vpll {
92 regulator-min-microvolt = <1050000>;
93 regulator-max-microvolt = <1800000>;
94 regulator-boot-on;
95 regulator-always-on;
96 };
97
98 vdig_reg: vdig {
99 regulator-min-microvolt = <1650000>;
100 regulator-max-microvolt = <1650000>;
101 regulator-boot-on;
102 };
103
104 vsd_reg: vsd {
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <3150000>;
107 };
108
109 vusb2_reg: vusb2 {
110 regulator-min-microvolt = <2400000>;
111 regulator-max-microvolt = <2775000>;
112 regulator-boot-on;
113 regulator-always-on;
114 };
115
116 vvideo_reg: vvideo {
117 regulator-min-microvolt = <2775000>;
118 regulator-max-microvolt = <2775000>;
119 };
120
121 vaudio_reg: vaudio {
122 regulator-min-microvolt = <2300000>;
123 regulator-max-microvolt = <3000000>;
124 };
125
126 vcam_reg: vcam {
127 regulator-min-microvolt = <2500000>;
128 regulator-max-microvolt = <3000000>;
129 };
130
131 vgen1_reg: vgen1 {
132 regulator-min-microvolt = <1200000>;
133 regulator-max-microvolt = <1200000>;
134 };
135
136 vgen2_reg: vgen2 {
137 regulator-min-microvolt = <1200000>;
138 regulator-max-microvolt = <3150000>;
139 regulator-always-on;
140 };
141
142 vgen3_reg: vgen3 {
143 regulator-min-microvolt = <1800000>;
144 regulator-max-microvolt = <2900000>;
145 regulator-always-on;
146 };
147 };
61 }; 148 };
62 149
63 flash: at45db321d@1 { 150 flash: at45db321d@1 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index c3977e0478b9..ce1c8238c897 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -36,11 +36,13 @@
36 usdhc@02198000 { /* uSDHC3 */ 36 usdhc@02198000 { /* uSDHC3 */
37 cd-gpios = <&gpio6 11 0>; 37 cd-gpios = <&gpio6 11 0>;
38 wp-gpios = <&gpio6 14 0>; 38 wp-gpios = <&gpio6 14 0>;
39 vmmc-supply = <&reg_3p3v>;
39 status = "okay"; 40 status = "okay";
40 }; 41 };
41 42
42 usdhc@0219c000 { /* uSDHC4 */ 43 usdhc@0219c000 { /* uSDHC4 */
43 fsl,card-wired; 44 fsl,card-wired;
45 vmmc-supply = <&reg_3p3v>;
44 status = "okay"; 46 status = "okay";
45 }; 47 };
46 48
@@ -50,6 +52,18 @@
50 }; 52 };
51 }; 53 };
52 54
55 regulators {
56 compatible = "simple-bus";
57
58 reg_3p3v: 3p3v {
59 compatible = "regulator-fixed";
60 regulator-name = "3P3V";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-always-on;
64 };
65 };
66
53 leds { 67 leds {
54 compatible = "gpio-leds"; 68 compatible = "gpio-leds";
55 69
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 08d920de7286..4663a4e5a285 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -32,18 +32,52 @@
32 usdhc@02198000 { /* uSDHC3 */ 32 usdhc@02198000 { /* uSDHC3 */
33 cd-gpios = <&gpio7 0 0>; 33 cd-gpios = <&gpio7 0 0>;
34 wp-gpios = <&gpio7 1 0>; 34 wp-gpios = <&gpio7 1 0>;
35 vmmc-supply = <&reg_3p3v>;
35 status = "okay"; 36 status = "okay";
36 }; 37 };
37 38
38 usdhc@0219c000 { /* uSDHC4 */ 39 usdhc@0219c000 { /* uSDHC4 */
39 cd-gpios = <&gpio2 6 0>; 40 cd-gpios = <&gpio2 6 0>;
40 wp-gpios = <&gpio2 7 0>; 41 wp-gpios = <&gpio2 7 0>;
42 vmmc-supply = <&reg_3p3v>;
41 status = "okay"; 43 status = "okay";
42 }; 44 };
43 45
44 uart2: uart@021e8000 { 46 uart2: uart@021e8000 {
45 status = "okay"; 47 status = "okay";
46 }; 48 };
49
50 i2c@021a0000 { /* I2C1 */
51 status = "okay";
52 clock-frequency = <100000>;
53
54 codec: sgtl5000@0a {
55 compatible = "fsl,sgtl5000";
56 reg = <0x0a>;
57 VDDA-supply = <&reg_2p5v>;
58 VDDIO-supply = <&reg_3p3v>;
59 };
60 };
61 };
62 };
63
64 regulators {
65 compatible = "simple-bus";
66
67 reg_2p5v: 2p5v {
68 compatible = "regulator-fixed";
69 regulator-name = "2P5V";
70 regulator-min-microvolt = <2500000>;
71 regulator-max-microvolt = <2500000>;
72 regulator-always-on;
73 };
74
75 reg_3p3v: 3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "3P3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
47 }; 81 };
48 }; 82 };
49}; 83};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9486be62bcdd..9f72cd4cf308 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -13,15 +13,6 @@
13 model = "TI OMAP3 BeagleBoard"; 13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle", "ti,omap3";
15 15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
23 };
24
25 memory { 16 memory {
26 device_type = "memory"; 17 device_type = "memory";
27 reg = <0x80000000 0x20000000>; /* 512 MB */ 18 reg = <0x80000000 0x20000000>; /* 512 MB */
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
new file mode 100644
index 000000000000..2eee16ec59b4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
14 compatible = "ti,omap3-evm", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 216c3317461d..c6121357c1eb 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,34 +61,57 @@
61 ranges; 61 ranges;
62 ti,hwmods = "l3_main"; 62 ti,hwmods = "l3_main";
63 63
64 intc: interrupt-controller@1 { 64 intc: interrupt-controller@48200000 {
65 compatible = "ti,omap3-intc"; 65 compatible = "ti,omap2-intc";
66 interrupt-controller; 66 interrupt-controller;
67 #interrupt-cells = <1>; 67 #interrupt-cells = <1>;
68 ti,intc-size = <96>;
69 reg = <0x48200000 0x1000>;
68 }; 70 };
69 71
70 uart1: serial@0x4806a000 { 72 uart1: serial@4806a000 {
71 compatible = "ti,omap3-uart"; 73 compatible = "ti,omap3-uart";
72 ti,hwmods = "uart1"; 74 ti,hwmods = "uart1";
73 clock-frequency = <48000000>; 75 clock-frequency = <48000000>;
74 }; 76 };
75 77
76 uart2: serial@0x4806c000 { 78 uart2: serial@4806c000 {
77 compatible = "ti,omap3-uart"; 79 compatible = "ti,omap3-uart";
78 ti,hwmods = "uart2"; 80 ti,hwmods = "uart2";
79 clock-frequency = <48000000>; 81 clock-frequency = <48000000>;
80 }; 82 };
81 83
82 uart3: serial@0x49020000 { 84 uart3: serial@49020000 {
83 compatible = "ti,omap3-uart"; 85 compatible = "ti,omap3-uart";
84 ti,hwmods = "uart3"; 86 ti,hwmods = "uart3";
85 clock-frequency = <48000000>; 87 clock-frequency = <48000000>;
86 }; 88 };
87 89
88 uart4: serial@0x49042000 { 90 uart4: serial@49042000 {
89 compatible = "ti,omap3-uart"; 91 compatible = "ti,omap3-uart";
90 ti,hwmods = "uart4"; 92 ti,hwmods = "uart4";
91 clock-frequency = <48000000>; 93 clock-frequency = <48000000>;
92 }; 94 };
95
96 i2c1: i2c@48070000 {
97 compatible = "ti,omap3-i2c";
98 #address-cells = <1>;
99 #size-cells = <0>;
100 ti,hwmods = "i2c1";
101 };
102
103 i2c2: i2c@48072000 {
104 compatible = "ti,omap3-i2c";
105 #address-cells = <1>;
106 #size-cells = <0>;
107 ti,hwmods = "i2c2";
108 };
109
110 i2c3: i2c@48060000 {
111 compatible = "ti,omap3-i2c";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 ti,hwmods = "i2c3";
115 };
93 }; 116 };
94}; 117};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index c7026578ce7d..9755ad5917f8 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -13,15 +13,6 @@
13 model = "TI OMAP4 PandaBoard"; 13 model = "TI OMAP4 PandaBoard";
14 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; 14 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
15 15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
23 };
24
25 memory { 16 memory {
26 device_type = "memory"; 17 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 066e28c90328..63c6b2b2bf42 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -13,15 +13,6 @@
13 model = "TI OMAP4 SDP board"; 13 model = "TI OMAP4 SDP board";
14 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; 14 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
15 15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
23 };
24
25 memory { 16 memory {
26 device_type = "memory"; 17 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1 GB */ 18 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index e8fe75fac7c5..3d35559e77bc 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -99,33 +99,61 @@
99 gic: interrupt-controller@48241000 { 99 gic: interrupt-controller@48241000 {
100 compatible = "arm,cortex-a9-gic"; 100 compatible = "arm,cortex-a9-gic";
101 interrupt-controller; 101 interrupt-controller;
102 #interrupt-cells = <1>; 102 #interrupt-cells = <3>;
103 reg = <0x48241000 0x1000>, 103 reg = <0x48241000 0x1000>,
104 <0x48240100 0x0100>; 104 <0x48240100 0x0100>;
105 }; 105 };
106 106
107 uart1: serial@0x4806a000 { 107 uart1: serial@4806a000 {
108 compatible = "ti,omap4-uart"; 108 compatible = "ti,omap4-uart";
109 ti,hwmods = "uart1"; 109 ti,hwmods = "uart1";
110 clock-frequency = <48000000>; 110 clock-frequency = <48000000>;
111 }; 111 };
112 112
113 uart2: serial@0x4806c000 { 113 uart2: serial@4806c000 {
114 compatible = "ti,omap4-uart"; 114 compatible = "ti,omap4-uart";
115 ti,hwmods = "uart2"; 115 ti,hwmods = "uart2";
116 clock-frequency = <48000000>; 116 clock-frequency = <48000000>;
117 }; 117 };
118 118
119 uart3: serial@0x48020000 { 119 uart3: serial@48020000 {
120 compatible = "ti,omap4-uart"; 120 compatible = "ti,omap4-uart";
121 ti,hwmods = "uart3"; 121 ti,hwmods = "uart3";
122 clock-frequency = <48000000>; 122 clock-frequency = <48000000>;
123 }; 123 };
124 124
125 uart4: serial@0x4806e000 { 125 uart4: serial@4806e000 {
126 compatible = "ti,omap4-uart"; 126 compatible = "ti,omap4-uart";
127 ti,hwmods = "uart4"; 127 ti,hwmods = "uart4";
128 clock-frequency = <48000000>; 128 clock-frequency = <48000000>;
129 }; 129 };
130
131 i2c1: i2c@48070000 {
132 compatible = "ti,omap4-i2c";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 ti,hwmods = "i2c1";
136 };
137
138 i2c2: i2c@48072000 {
139 compatible = "ti,omap4-i2c";
140 #address-cells = <1>;
141 #size-cells = <0>;
142 ti,hwmods = "i2c2";
143 };
144
145 i2c3: i2c@48060000 {
146 compatible = "ti,omap4-i2c";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 ti,hwmods = "i2c3";
150 };
151
152 i2c4: i2c@48350000 {
153 compatible = "ti,omap4-i2c";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 ti,hwmods = "i2c4";
157 };
130 }; 158 };
131}; 159};
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644
index 000000000000..e762facb3fa4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "pxa168.dtsi"
12
13/ {
14 model = "Marvell PXA168 Aspenite Development Board";
15 compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x04000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart1: uart@d4017000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644
index 000000000000..d32d5128f225
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
21 intc: intc-interrupt-controller@d4282000 {
22 compatible = "mrvl,mmp-intc", "mrvl,intc";
23 interrupt-controller;
24 #interrupt-cells = <1>;
25 reg = <0xd4282000 0x1000>;
26 };
27
28 soc {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 interrupt-parent = <&intc>;
33 ranges;
34
35 apb@d4000000 { /* APB */
36 compatible = "mrvl,apb-bus", "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xd4000000 0x00200000>;
40 ranges;
41
42 uart1: uart@d4017000 {
43 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
44 reg = <0xd4017000 0x1000>;
45 interrupts = <27>;
46 status = "disabled";
47 };
48
49 uart2: uart@d4018000 {
50 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
51 reg = <0xd4018000 0x1000>;
52 interrupts = <28>;
53 status = "disabled";
54 };
55
56 uart3: uart@d4026000 {
57 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
58 reg = <0xd4026000 0x1000>;
59 interrupts = <29>;
60 status = "disabled";
61 };
62
63 gpio: gpio@d4019000 {
64 compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
65 reg = <0xd4019000 0x1000>;
66 interrupts = <49>;
67 interrupt-names = "gpio_mux";
68 gpio-controller;
69 #gpio-cells = <1>;
70 interrupt-controller;
71 #interrupt-cells = <1>;
72 };
73
74 twsi1: i2c@d4011000 {
75 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
76 reg = <0xd4011000 0x1000>;
77 interrupts = <7>;
78 mrvl,i2c-fast-mode;
79 status = "disabled";
80 };
81
82 twsi2: i2c@d4025000 {
83 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
84 reg = <0xd4025000 0x1000>;
85 interrupts = <58>;
86 status = "disabled";
87 };
88
89 rtc: rtc@d4010000 {
90 compatible = "mrvl,mmp-rtc";
91 reg = <0xd4010000 0x1000>;
92 interrupts = <5 6>;
93 interrupt-names = "rtc 1Hz", "rtc alarm";
94 status = "disabled";
95 };
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 70c41fc897d7..73263501f581 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -33,4 +33,22 @@
33 i2c@7000d000 { 33 i2c@7000d000 {
34 clock-frequency = <100000>; 34 clock-frequency = <100000>;
35 }; 35 };
36
37 sdhci@78000000 {
38 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
39 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
40 power-gpios = <&gpio 31 0>; /* gpio PD7 */
41 };
42
43 sdhci@78000200 {
44 status = "disable";
45 };
46
47 sdhci@78000400 {
48 status = "disable";
49 };
50
51 sdhci@78000400 {
52 support-8bit;
53 };
36}; 54};
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index fc97254c3644..6c02abb469d4 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -65,7 +65,8 @@
65 "Headset Mic", "MICBIAS1", 65 "Headset Mic", "MICBIAS1",
66 "MIC1", "Headset Mic", 66 "MIC1", "Headset Mic",
67 "Headset Stereophone", "HPR", 67 "Headset Stereophone", "HPR",
68 "Headset Stereophone", "HPL"; 68 "Headset Stereophone", "HPL",
69 "DMICDAT", "Digital Mic";
69 70
70 nvidia,audio-codec = <&alc5632>; 71 nvidia,audio-codec = <&alc5632>;
71 nvidia,i2s-controller = <&tegra_i2s1>; 72 nvidia,i2s-controller = <&tegra_i2s1>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ec1f0101c79c..aff8a175aa40 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -17,6 +17,12 @@
17 < 0x50040100 0x0100 >; 17 < 0x50040100 0x0100 >;
18 }; 18 };
19 19
20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
20 apbdma: dma@6000a000 { 26 apbdma: dma@6000a000 {
21 compatible = "nvidia,tegra20-apbdma"; 27 compatible = "nvidia,tegra20-apbdma";
22 reg = <0x6000a000 0x1200>; 28 reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ac4b75cb26c0..62a7b39f1c9a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -17,6 +17,14 @@
17 < 0x50040100 0x0100 >; 17 < 0x50040100 0x0100 >;
18 }; 18 };
19 19
20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
20 apbdma: dma@6000a000 { 28 apbdma: dma@6000a000 {
21 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
22 reg = <0x6000a000 0x1400>; 30 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index f04b535477f5..d74545a2a77c 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -32,4 +32,27 @@
32 }; 32 };
33 }; 33 };
34 }; 34 };
35
36 leds {
37 compatible = "gpio-leds";
38
39 user_led {
40 label = "user_led";
41 gpios = <&pioB 21 1>;
42 linux,default-trigger = "heartbeat";
43 };
44 };
45
46 gpio_keys {
47 compatible = "gpio-keys";
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 user_pb {
52 label = "user_pb";
53 gpios = <&pioB 10 1>;
54 linux,code = <28>;
55 gpio-key,wakeup;
56 };
57 };
35}; 58};
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000000000000..16076e2d0934
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard {
26 compatible = "simple-bus";
27 arm,v2m-memory-map = "rs1";
28 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31
32 flash@0,00000000 {
33 compatible = "arm,vexpress-flash", "cfi-flash";
34 reg = <0 0x00000000 0x04000000>,
35 <4 0x00000000 0x04000000>;
36 bank-width = <4>;
37 };
38
39 psram@1,00000000 {
40 compatible = "arm,vexpress-psram", "mtd-ram";
41 reg = <1 0x00000000 0x02000000>;
42 bank-width = <4>;
43 };
44
45 vram@2,00000000 {
46 compatible = "arm,vexpress-vram";
47 reg = <2 0x00000000 0x00800000>;
48 };
49
50 ethernet@2,02000000 {
51 compatible = "smsc,lan9118", "smsc,lan9115";
52 reg = <2 0x02000000 0x10000>;
53 interrupts = <15>;
54 phy-mode = "mii";
55 reg-io-width = <4>;
56 smsc,irq-active-high;
57 smsc,irq-push-pull;
58 };
59
60 usb@2,03000000 {
61 compatible = "nxp,usb-isp1761";
62 reg = <2 0x03000000 0x20000>;
63 interrupts = <16>;
64 port1-otg;
65 };
66
67 iofpga@3,00000000 {
68 compatible = "arm,amba-bus", "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 3 0 0x200000>;
72
73 sysreg@010000 {
74 compatible = "arm,vexpress-sysreg";
75 reg = <0x010000 0x1000>;
76 };
77
78 sysctl@020000 {
79 compatible = "arm,sp810", "arm,primecell";
80 reg = <0x020000 0x1000>;
81 };
82
83 /* PCI-E I2C bus */
84 v2m_i2c_pcie: i2c@030000 {
85 compatible = "arm,versatile-i2c";
86 reg = <0x030000 0x1000>;
87
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 pcie-switch@60 {
92 compatible = "idt,89hpes32h8";
93 reg = <0x60>;
94 };
95 };
96
97 aaci@040000 {
98 compatible = "arm,pl041", "arm,primecell";
99 reg = <0x040000 0x1000>;
100 interrupts = <11>;
101 };
102
103 mmci@050000 {
104 compatible = "arm,pl180", "arm,primecell";
105 reg = <0x050000 0x1000>;
106 interrupts = <9 10>;
107 };
108
109 kmi@060000 {
110 compatible = "arm,pl050", "arm,primecell";
111 reg = <0x060000 0x1000>;
112 interrupts = <12>;
113 };
114
115 kmi@070000 {
116 compatible = "arm,pl050", "arm,primecell";
117 reg = <0x070000 0x1000>;
118 interrupts = <13>;
119 };
120
121 v2m_serial0: uart@090000 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x090000 0x1000>;
124 interrupts = <5>;
125 };
126
127 v2m_serial1: uart@0a0000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0a0000 0x1000>;
130 interrupts = <6>;
131 };
132
133 v2m_serial2: uart@0b0000 {
134 compatible = "arm,pl011", "arm,primecell";
135 reg = <0x0b0000 0x1000>;
136 interrupts = <7>;
137 };
138
139 v2m_serial3: uart@0c0000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0x0c0000 0x1000>;
142 interrupts = <8>;
143 };
144
145 wdt@0f0000 {
146 compatible = "arm,sp805", "arm,primecell";
147 reg = <0x0f0000 0x1000>;
148 interrupts = <0>;
149 };
150
151 v2m_timer01: timer@110000 {
152 compatible = "arm,sp804", "arm,primecell";
153 reg = <0x110000 0x1000>;
154 interrupts = <2>;
155 };
156
157 v2m_timer23: timer@120000 {
158 compatible = "arm,sp804", "arm,primecell";
159 reg = <0x120000 0x1000>;
160 };
161
162 /* DVI I2C bus */
163 v2m_i2c_dvi: i2c@160000 {
164 compatible = "arm,versatile-i2c";
165 reg = <0x160000 0x1000>;
166
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 dvi-transmitter@39 {
171 compatible = "sil,sii9022-tpi", "sil,sii9022";
172 reg = <0x39>;
173 };
174
175 dvi-transmitter@60 {
176 compatible = "sil,sii9022-cpi", "sil,sii9022";
177 reg = <0x60>;
178 };
179 };
180
181 rtc@170000 {
182 compatible = "arm,pl031", "arm,primecell";
183 reg = <0x170000 0x1000>;
184 interrupts = <4>;
185 };
186
187 compact-flash@1a0000 {
188 compatible = "arm,vexpress-cf", "ata-generic";
189 reg = <0x1a0000 0x100
190 0x1a0100 0xf00>;
191 reg-shift = <2>;
192 };
193
194 clcd@1f0000 {
195 compatible = "arm,pl111", "arm,primecell";
196 reg = <0x1f0000 0x1000>;
197 interrupts = <14>;
198 };
199 };
200 };
201};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 000000000000..a6c9c7c82d53
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,200 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * Original memory map ("Legacy memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m-rs1.dtsi!
18 */
19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard {
26 compatible = "simple-bus";
27 #address-cells = <2>; /* SMB chipselect number and offset */
28 #size-cells = <1>;
29 #interrupt-cells = <1>;
30
31 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash";
33 reg = <0 0x00000000 0x04000000>,
34 <1 0x00000000 0x04000000>;
35 bank-width = <4>;
36 };
37
38 psram@2,00000000 {
39 compatible = "arm,vexpress-psram", "mtd-ram";
40 reg = <2 0x00000000 0x02000000>;
41 bank-width = <4>;
42 };
43
44 vram@3,00000000 {
45 compatible = "arm,vexpress-vram";
46 reg = <3 0x00000000 0x00800000>;
47 };
48
49 ethernet@3,02000000 {
50 compatible = "smsc,lan9118", "smsc,lan9115";
51 reg = <3 0x02000000 0x10000>;
52 interrupts = <15>;
53 phy-mode = "mii";
54 reg-io-width = <4>;
55 smsc,irq-active-high;
56 smsc,irq-push-pull;
57 };
58
59 usb@3,03000000 {
60 compatible = "nxp,usb-isp1761";
61 reg = <3 0x03000000 0x20000>;
62 interrupts = <16>;
63 port1-otg;
64 };
65
66 iofpga@7,00000000 {
67 compatible = "arm,amba-bus", "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges = <0 7 0 0x20000>;
71
72 sysreg@00000 {
73 compatible = "arm,vexpress-sysreg";
74 reg = <0x00000 0x1000>;
75 };
76
77 sysctl@01000 {
78 compatible = "arm,sp810", "arm,primecell";
79 reg = <0x01000 0x1000>;
80 };
81
82 /* PCI-E I2C bus */
83 v2m_i2c_pcie: i2c@02000 {
84 compatible = "arm,versatile-i2c";
85 reg = <0x02000 0x1000>;
86
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 pcie-switch@60 {
91 compatible = "idt,89hpes32h8";
92 reg = <0x60>;
93 };
94 };
95
96 aaci@04000 {
97 compatible = "arm,pl041", "arm,primecell";
98 reg = <0x04000 0x1000>;
99 interrupts = <11>;
100 };
101
102 mmci@05000 {
103 compatible = "arm,pl180", "arm,primecell";
104 reg = <0x05000 0x1000>;
105 interrupts = <9 10>;
106 };
107
108 kmi@06000 {
109 compatible = "arm,pl050", "arm,primecell";
110 reg = <0x06000 0x1000>;
111 interrupts = <12>;
112 };
113
114 kmi@07000 {
115 compatible = "arm,pl050", "arm,primecell";
116 reg = <0x07000 0x1000>;
117 interrupts = <13>;
118 };
119
120 v2m_serial0: uart@09000 {
121 compatible = "arm,pl011", "arm,primecell";
122 reg = <0x09000 0x1000>;
123 interrupts = <5>;
124 };
125
126 v2m_serial1: uart@0a000 {
127 compatible = "arm,pl011", "arm,primecell";
128 reg = <0x0a000 0x1000>;
129 interrupts = <6>;
130 };
131
132 v2m_serial2: uart@0b000 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0x0b000 0x1000>;
135 interrupts = <7>;
136 };
137
138 v2m_serial3: uart@0c000 {
139 compatible = "arm,pl011", "arm,primecell";
140 reg = <0x0c000 0x1000>;
141 interrupts = <8>;
142 };
143
144 wdt@0f000 {
145 compatible = "arm,sp805", "arm,primecell";
146 reg = <0x0f000 0x1000>;
147 interrupts = <0>;
148 };
149
150 v2m_timer01: timer@11000 {
151 compatible = "arm,sp804", "arm,primecell";
152 reg = <0x11000 0x1000>;
153 interrupts = <2>;
154 };
155
156 v2m_timer23: timer@12000 {
157 compatible = "arm,sp804", "arm,primecell";
158 reg = <0x12000 0x1000>;
159 };
160
161 /* DVI I2C bus */
162 v2m_i2c_dvi: i2c@16000 {
163 compatible = "arm,versatile-i2c";
164 reg = <0x16000 0x1000>;
165
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 dvi-transmitter@39 {
170 compatible = "sil,sii9022-tpi", "sil,sii9022";
171 reg = <0x39>;
172 };
173
174 dvi-transmitter@60 {
175 compatible = "sil,sii9022-cpi", "sil,sii9022";
176 reg = <0x60>;
177 };
178 };
179
180 rtc@17000 {
181 compatible = "arm,pl031", "arm,primecell";
182 reg = <0x17000 0x1000>;
183 interrupts = <4>;
184 };
185
186 compact-flash@1a000 {
187 compatible = "arm,vexpress-cf", "ata-generic";
188 reg = <0x1a000 0x100
189 0x1a100 0xf00>;
190 reg-shift = <2>;
191 };
192
193 clcd@1f000 {
194 compatible = "arm,pl111", "arm,primecell";
195 reg = <0x1f000 0x1000>;
196 interrupts = <14>;
197 };
198 };
199 };
200};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 000000000000..941b161ab78c
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,157 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 (version with Test Chip 1)
5 * Cortex-A15 MPCore (V2P-CA15)
6 *
7 * HBI-0237A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15";
14 arm,hbi = <0x237>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 };
40
41 cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <1>;
45 };
46 };
47
48 memory@80000000 {
49 device_type = "memory";
50 reg = <0x80000000 0x40000000>;
51 };
52
53 hdlcd@2b000000 {
54 compatible = "arm,hdlcd";
55 reg = <0x2b000000 0x1000>;
56 interrupts = <0 85 4>;
57 };
58
59 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell";
61 reg = <0x2b0a0000 0x1000>;
62 };
63
64 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell";
66 reg = <0x2b060000 0x1000>;
67 interrupts = <98>;
68 };
69
70 gic: interrupt-controller@2c001000 {
71 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
72 #interrupt-cells = <3>;
73 #address-cells = <0>;
74 interrupt-controller;
75 reg = <0x2c001000 0x1000>,
76 <0x2c002000 0x100>;
77 };
78
79 memory-controller@7ffd0000 {
80 compatible = "arm,pl354", "arm,primecell";
81 reg = <0x7ffd0000 0x1000>;
82 interrupts = <0 86 4>,
83 <0 87 4>;
84 };
85
86 dma@7ffb0000 {
87 compatible = "arm,pl330", "arm,primecell";
88 reg = <0x7ffb0000 0x1000>;
89 interrupts = <0 92 4>,
90 <0 88 4>,
91 <0 89 4>,
92 <0 90 4>,
93 <0 91 4>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
98 interrupts = <0 68 4>,
99 <0 69 4>;
100 };
101
102 motherboard {
103 ranges = <0 0 0x08000000 0x04000000>,
104 <1 0 0x14000000 0x04000000>,
105 <2 0 0x18000000 0x04000000>,
106 <3 0 0x1c000000 0x04000000>,
107 <4 0 0x0c000000 0x04000000>,
108 <5 0 0x10000000 0x04000000>;
109
110 interrupt-map-mask = <0 0 63>;
111 interrupt-map = <0 0 0 &gic 0 0 4>,
112 <0 0 1 &gic 0 1 4>,
113 <0 0 2 &gic 0 2 4>,
114 <0 0 3 &gic 0 3 4>,
115 <0 0 4 &gic 0 4 4>,
116 <0 0 5 &gic 0 5 4>,
117 <0 0 6 &gic 0 6 4>,
118 <0 0 7 &gic 0 7 4>,
119 <0 0 8 &gic 0 8 4>,
120 <0 0 9 &gic 0 9 4>,
121 <0 0 10 &gic 0 10 4>,
122 <0 0 11 &gic 0 11 4>,
123 <0 0 12 &gic 0 12 4>,
124 <0 0 13 &gic 0 13 4>,
125 <0 0 14 &gic 0 14 4>,
126 <0 0 15 &gic 0 15 4>,
127 <0 0 16 &gic 0 16 4>,
128 <0 0 17 &gic 0 17 4>,
129 <0 0 18 &gic 0 18 4>,
130 <0 0 19 &gic 0 19 4>,
131 <0 0 20 &gic 0 20 4>,
132 <0 0 21 &gic 0 21 4>,
133 <0 0 22 &gic 0 22 4>,
134 <0 0 23 &gic 0 23 4>,
135 <0 0 24 &gic 0 24 4>,
136 <0 0 25 &gic 0 25 4>,
137 <0 0 26 &gic 0 26 4>,
138 <0 0 27 &gic 0 27 4>,
139 <0 0 28 &gic 0 28 4>,
140 <0 0 29 &gic 0 29 4>,
141 <0 0 30 &gic 0 30 4>,
142 <0 0 31 &gic 0 31 4>,
143 <0 0 32 &gic 0 32 4>,
144 <0 0 33 &gic 0 33 4>,
145 <0 0 34 &gic 0 34 4>,
146 <0 0 35 &gic 0 35 4>,
147 <0 0 36 &gic 0 36 4>,
148 <0 0 37 &gic 0 37 4>,
149 <0 0 38 &gic 0 38 4>,
150 <0 0 39 &gic 0 39 4>,
151 <0 0 40 &gic 0 40 4>,
152 <0 0 41 &gic 0 41 4>,
153 <0 0 42 &gic 0 42 4>;
154 };
155};
156
157/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000000000000..6905e66d4748
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,162 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A5x2
5 * Cortex-A5 MPCore (V2P-CA5s)
6 *
7 * HBI-0225B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA5s";
14 arm,hbi = <0x225>;
15 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a5";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a5";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory@80000000 {
51 device_type = "memory";
52 reg = <0x80000000 0x40000000>;
53 };
54
55 hdlcd@2a110000 {
56 compatible = "arm,hdlcd";
57 reg = <0x2a110000 0x1000>;
58 interrupts = <0 85 4>;
59 };
60
61 memory-controller@2a150000 {
62 compatible = "arm,pl341", "arm,primecell";
63 reg = <0x2a150000 0x1000>;
64 };
65
66 memory-controller@2a190000 {
67 compatible = "arm,pl354", "arm,primecell";
68 reg = <0x2a190000 0x1000>;
69 interrupts = <0 86 4>,
70 <0 87 4>;
71 };
72
73 scu@2c000000 {
74 compatible = "arm,cortex-a5-scu";
75 reg = <0x2c000000 0x58>;
76 };
77
78 timer@2c000600 {
79 compatible = "arm,cortex-a5-twd-timer";
80 reg = <0x2c000600 0x38>;
81 interrupts = <1 2 0x304>,
82 <1 3 0x304>;
83 };
84
85 gic: interrupt-controller@2c001000 {
86 compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 #address-cells = <0>;
89 interrupt-controller;
90 reg = <0x2c001000 0x1000>,
91 <0x2c000100 0x100>;
92 };
93
94 L2: cache-controller@2c0f0000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x2c0f0000 0x1000>;
97 interrupts = <0 84 4>;
98 cache-level = <2>;
99 };
100
101 pmu {
102 compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
103 interrupts = <0 68 4>,
104 <0 69 4>;
105 };
106
107 motherboard {
108 ranges = <0 0 0x08000000 0x04000000>,
109 <1 0 0x14000000 0x04000000>,
110 <2 0 0x18000000 0x04000000>,
111 <3 0 0x1c000000 0x04000000>,
112 <4 0 0x0c000000 0x04000000>,
113 <5 0 0x10000000 0x04000000>;
114
115 interrupt-map-mask = <0 0 63>;
116 interrupt-map = <0 0 0 &gic 0 0 4>,
117 <0 0 1 &gic 0 1 4>,
118 <0 0 2 &gic 0 2 4>,
119 <0 0 3 &gic 0 3 4>,
120 <0 0 4 &gic 0 4 4>,
121 <0 0 5 &gic 0 5 4>,
122 <0 0 6 &gic 0 6 4>,
123 <0 0 7 &gic 0 7 4>,
124 <0 0 8 &gic 0 8 4>,
125 <0 0 9 &gic 0 9 4>,
126 <0 0 10 &gic 0 10 4>,
127 <0 0 11 &gic 0 11 4>,
128 <0 0 12 &gic 0 12 4>,
129 <0 0 13 &gic 0 13 4>,
130 <0 0 14 &gic 0 14 4>,
131 <0 0 15 &gic 0 15 4>,
132 <0 0 16 &gic 0 16 4>,
133 <0 0 17 &gic 0 17 4>,
134 <0 0 18 &gic 0 18 4>,
135 <0 0 19 &gic 0 19 4>,
136 <0 0 20 &gic 0 20 4>,
137 <0 0 21 &gic 0 21 4>,
138 <0 0 22 &gic 0 22 4>,
139 <0 0 23 &gic 0 23 4>,
140 <0 0 24 &gic 0 24 4>,
141 <0 0 25 &gic 0 25 4>,
142 <0 0 26 &gic 0 26 4>,
143 <0 0 27 &gic 0 27 4>,
144 <0 0 28 &gic 0 28 4>,
145 <0 0 29 &gic 0 29 4>,
146 <0 0 30 &gic 0 30 4>,
147 <0 0 31 &gic 0 31 4>,
148 <0 0 32 &gic 0 32 4>,
149 <0 0 33 &gic 0 33 4>,
150 <0 0 34 &gic 0 34 4>,
151 <0 0 35 &gic 0 35 4>,
152 <0 0 36 &gic 0 36 4>,
153 <0 0 37 &gic 0 37 4>,
154 <0 0 38 &gic 0 38 4>,
155 <0 0 39 &gic 0 39 4>,
156 <0 0 40 &gic 0 40 4>,
157 <0 0 41 &gic 0 41 4>,
158 <0 0 42 &gic 0 42 4>;
159 };
160};
161
162/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 000000000000..da778693be54
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,192 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A9x4
5 * Cortex-A9 MPCore (V2P-CA9)
6 *
7 * HBI-0191B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA9";
14 arm,hbi = <0x191>;
15 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 };
48
49 cpu@2 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a9";
52 reg = <2>;
53 next-level-cache = <&L2>;
54 };
55
56 cpu@3 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 reg = <3>;
60 next-level-cache = <&L2>;
61 };
62 };
63
64 memory@60000000 {
65 device_type = "memory";
66 reg = <0x60000000 0x40000000>;
67 };
68
69 clcd@10020000 {
70 compatible = "arm,pl111", "arm,primecell";
71 reg = <0x10020000 0x1000>;
72 interrupts = <0 44 4>;
73 };
74
75 memory-controller@100e0000 {
76 compatible = "arm,pl341", "arm,primecell";
77 reg = <0x100e0000 0x1000>;
78 };
79
80 memory-controller@100e1000 {
81 compatible = "arm,pl354", "arm,primecell";
82 reg = <0x100e1000 0x1000>;
83 interrupts = <0 45 4>,
84 <0 46 4>;
85 };
86
87 timer@100e4000 {
88 compatible = "arm,sp804", "arm,primecell";
89 reg = <0x100e4000 0x1000>;
90 interrupts = <0 48 4>,
91 <0 49 4>;
92 };
93
94 watchdog@100e5000 {
95 compatible = "arm,sp805", "arm,primecell";
96 reg = <0x100e5000 0x1000>;
97 interrupts = <0 51 4>;
98 };
99
100 scu@1e000000 {
101 compatible = "arm,cortex-a9-scu";
102 reg = <0x1e000000 0x58>;
103 };
104
105 timer@1e000600 {
106 compatible = "arm,cortex-a9-twd-timer";
107 reg = <0x1e000600 0x20>;
108 interrupts = <1 2 0xf04>,
109 <1 3 0xf04>;
110 };
111
112 gic: interrupt-controller@1e001000 {
113 compatible = "arm,cortex-a9-gic";
114 #interrupt-cells = <3>;
115 #address-cells = <0>;
116 interrupt-controller;
117 reg = <0x1e001000 0x1000>,
118 <0x1e000100 0x100>;
119 };
120
121 L2: cache-controller@1e00a000 {
122 compatible = "arm,pl310-cache";
123 reg = <0x1e00a000 0x1000>;
124 interrupts = <0 43 4>;
125 cache-level = <2>;
126 arm,data-latency = <1 1 1>;
127 arm,tag-latency = <1 1 1>;
128 };
129
130 pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupts = <0 60 4>,
133 <0 61 4>,
134 <0 62 4>,
135 <0 63 4>;
136 };
137
138 motherboard {
139 ranges = <0 0 0x40000000 0x04000000>,
140 <1 0 0x44000000 0x04000000>,
141 <2 0 0x48000000 0x04000000>,
142 <3 0 0x4c000000 0x04000000>,
143 <7 0 0x10000000 0x00020000>;
144
145 interrupt-map-mask = <0 0 63>;
146 interrupt-map = <0 0 0 &gic 0 0 4>,
147 <0 0 1 &gic 0 1 4>,
148 <0 0 2 &gic 0 2 4>,
149 <0 0 3 &gic 0 3 4>,
150 <0 0 4 &gic 0 4 4>,
151 <0 0 5 &gic 0 5 4>,
152 <0 0 6 &gic 0 6 4>,
153 <0 0 7 &gic 0 7 4>,
154 <0 0 8 &gic 0 8 4>,
155 <0 0 9 &gic 0 9 4>,
156 <0 0 10 &gic 0 10 4>,
157 <0 0 11 &gic 0 11 4>,
158 <0 0 12 &gic 0 12 4>,
159 <0 0 13 &gic 0 13 4>,
160 <0 0 14 &gic 0 14 4>,
161 <0 0 15 &gic 0 15 4>,
162 <0 0 16 &gic 0 16 4>,
163 <0 0 17 &gic 0 17 4>,
164 <0 0 18 &gic 0 18 4>,
165 <0 0 19 &gic 0 19 4>,
166 <0 0 20 &gic 0 20 4>,
167 <0 0 21 &gic 0 21 4>,
168 <0 0 22 &gic 0 22 4>,
169 <0 0 23 &gic 0 23 4>,
170 <0 0 24 &gic 0 24 4>,
171 <0 0 25 &gic 0 25 4>,
172 <0 0 26 &gic 0 26 4>,
173 <0 0 27 &gic 0 27 4>,
174 <0 0 28 &gic 0 28 4>,
175 <0 0 29 &gic 0 29 4>,
176 <0 0 30 &gic 0 30 4>,
177 <0 0 31 &gic 0 31 4>,
178 <0 0 32 &gic 0 32 4>,
179 <0 0 33 &gic 0 33 4>,
180 <0 0 34 &gic 0 34 4>,
181 <0 0 35 &gic 0 35 4>,
182 <0 0 36 &gic 0 36 4>,
183 <0 0 37 &gic 0 37 4>,
184 <0 0 38 &gic 0 38 4>,
185 <0 0 39 &gic 0 39 4>,
186 <0 0 40 &gic 0 40 4>,
187 <0 0 41 &gic 0 41 4>,
188 <0 0 42 &gic 0 42 4>;
189 };
190};
191
192/include/ "vexpress-v2m.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 02:16:58 -0400