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authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>2015-02-16 11:58:50 -0500
committerSimon Horman <horms+renesas@verge.net.au>2015-02-23 16:40:47 -0500
commit66462be7c6f986903702505e98f42230e22bf4c7 (patch)
tree0b5494ae3f9003586b61e872f150704512af1bd0 /arch/arm/boot/dts
parent43cbec8577cfd66713416c3ad33a9856edcaffb9 (diff)
ARM: shmobile: r8a7778: add MSTP clock assignments to DT
Assigns clocks to i2c*, tmu*, scif*, mmcif, sdhi*, and hspi*. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 822ba9003138..5c347e8d7ded 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -133,6 +133,7 @@
133 compatible = "renesas,i2c-r8a7778"; 133 compatible = "renesas,i2c-r8a7778";
134 reg = <0xffc70000 0x1000>; 134 reg = <0xffc70000 0x1000>;
135 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 135 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
136 status = "disabled"; 137 status = "disabled";
137 }; 138 };
138 139
@@ -142,6 +143,7 @@
142 compatible = "renesas,i2c-r8a7778"; 143 compatible = "renesas,i2c-r8a7778";
143 reg = <0xffc71000 0x1000>; 144 reg = <0xffc71000 0x1000>;
144 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 145 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
145 status = "disabled"; 147 status = "disabled";
146 }; 148 };
147 149
@@ -151,6 +153,7 @@
151 compatible = "renesas,i2c-r8a7778"; 153 compatible = "renesas,i2c-r8a7778";
152 reg = <0xffc72000 0x1000>; 154 reg = <0xffc72000 0x1000>;
153 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 155 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
154 status = "disabled"; 157 status = "disabled";
155 }; 158 };
156 159
@@ -160,6 +163,7 @@
160 compatible = "renesas,i2c-r8a7778"; 163 compatible = "renesas,i2c-r8a7778";
161 reg = <0xffc73000 0x1000>; 164 reg = <0xffc73000 0x1000>;
162 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 165 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
163 status = "disabled"; 167 status = "disabled";
164 }; 168 };
165 169
@@ -169,6 +173,8 @@
169 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 173 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
170 <0 33 IRQ_TYPE_LEVEL_HIGH>, 174 <0 33 IRQ_TYPE_LEVEL_HIGH>,
171 <0 34 IRQ_TYPE_LEVEL_HIGH>; 175 <0 34 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
177 clock-names = "fck";
172 178
173 #renesas,channels = <3>; 179 #renesas,channels = <3>;
174 180
@@ -181,6 +187,8 @@
181 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 187 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
182 <0 37 IRQ_TYPE_LEVEL_HIGH>, 188 <0 37 IRQ_TYPE_LEVEL_HIGH>,
183 <0 38 IRQ_TYPE_LEVEL_HIGH>; 189 <0 38 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
191 clock-names = "fck";
184 192
185 #renesas,channels = <3>; 193 #renesas,channels = <3>;
186 194
@@ -193,6 +201,8 @@
193 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 201 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
194 <0 41 IRQ_TYPE_LEVEL_HIGH>, 202 <0 41 IRQ_TYPE_LEVEL_HIGH>,
195 <0 42 IRQ_TYPE_LEVEL_HIGH>; 203 <0 42 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
205 clock-names = "fck";
196 206
197 #renesas,channels = <3>; 207 #renesas,channels = <3>;
198 208
@@ -203,6 +213,8 @@
203 compatible = "renesas,scif-r8a7778", "renesas,scif"; 213 compatible = "renesas,scif-r8a7778", "renesas,scif";
204 reg = <0xffe40000 0x100>; 214 reg = <0xffe40000 0x100>;
205 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 215 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
217 clock-names = "sci_ick";
206 status = "disabled"; 218 status = "disabled";
207 }; 219 };
208 220
@@ -210,6 +222,8 @@
210 compatible = "renesas,scif-r8a7778", "renesas,scif"; 222 compatible = "renesas,scif-r8a7778", "renesas,scif";
211 reg = <0xffe41000 0x100>; 223 reg = <0xffe41000 0x100>;
212 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; 224 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
226 clock-names = "sci_ick";
213 status = "disabled"; 227 status = "disabled";
214 }; 228 };
215 229
@@ -217,6 +231,8 @@
217 compatible = "renesas,scif-r8a7778", "renesas,scif"; 231 compatible = "renesas,scif-r8a7778", "renesas,scif";
218 reg = <0xffe42000 0x100>; 232 reg = <0xffe42000 0x100>;
219 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 233 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
235 clock-names = "sci_ick";
220 status = "disabled"; 236 status = "disabled";
221 }; 237 };
222 238
@@ -224,6 +240,8 @@
224 compatible = "renesas,scif-r8a7778", "renesas,scif"; 240 compatible = "renesas,scif-r8a7778", "renesas,scif";
225 reg = <0xffe43000 0x100>; 241 reg = <0xffe43000 0x100>;
226 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 242 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
244 clock-names = "sci_ick";
227 status = "disabled"; 245 status = "disabled";
228 }; 246 };
229 247
@@ -231,6 +249,8 @@
231 compatible = "renesas,scif-r8a7778", "renesas,scif"; 249 compatible = "renesas,scif-r8a7778", "renesas,scif";
232 reg = <0xffe44000 0x100>; 250 reg = <0xffe44000 0x100>;
233 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 251 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
253 clock-names = "sci_ick";
234 status = "disabled"; 254 status = "disabled";
235 }; 255 };
236 256
@@ -238,6 +258,8 @@
238 compatible = "renesas,scif-r8a7778", "renesas,scif"; 258 compatible = "renesas,scif-r8a7778", "renesas,scif";
239 reg = <0xffe45000 0x100>; 259 reg = <0xffe45000 0x100>;
240 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 260 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
262 clock-names = "sci_ick";
241 status = "disabled"; 263 status = "disabled";
242 }; 264 };
243 265
@@ -245,6 +267,7 @@
245 compatible = "renesas,sh-mmcif"; 267 compatible = "renesas,sh-mmcif";
246 reg = <0xffe4e000 0x100>; 268 reg = <0xffe4e000 0x100>;
247 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 269 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
248 status = "disabled"; 271 status = "disabled";
249 }; 272 };
250 273
@@ -252,6 +275,7 @@
252 compatible = "renesas,sdhi-r8a7778"; 275 compatible = "renesas,sdhi-r8a7778";
253 reg = <0xffe4c000 0x100>; 276 reg = <0xffe4c000 0x100>;
254 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 277 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
255 status = "disabled"; 279 status = "disabled";
256 }; 280 };
257 281
@@ -259,6 +283,7 @@
259 compatible = "renesas,sdhi-r8a7778"; 283 compatible = "renesas,sdhi-r8a7778";
260 reg = <0xffe4d000 0x100>; 284 reg = <0xffe4d000 0x100>;
261 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 285 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
262 status = "disabled"; 287 status = "disabled";
263 }; 288 };
264 289
@@ -266,6 +291,7 @@
266 compatible = "renesas,sdhi-r8a7778"; 291 compatible = "renesas,sdhi-r8a7778";
267 reg = <0xffe4f000 0x100>; 292 reg = <0xffe4f000 0x100>;
268 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 293 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
269 status = "disabled"; 295 status = "disabled";
270 }; 296 };
271 297
@@ -273,6 +299,7 @@
273 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 299 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
274 reg = <0xfffc7000 0x18>; 300 reg = <0xfffc7000 0x18>;
275 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 301 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
276 #address-cells = <1>; 303 #address-cells = <1>;
277 #size-cells = <0>; 304 #size-cells = <0>;
278 status = "disabled"; 305 status = "disabled";
@@ -282,6 +309,7 @@
282 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 309 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
283 reg = <0xfffc8000 0x18>; 310 reg = <0xfffc8000 0x18>;
284 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 311 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
285 #address-cells = <1>; 313 #address-cells = <1>;
286 #size-cells = <0>; 314 #size-cells = <0>;
287 status = "disabled"; 315 status = "disabled";
@@ -291,6 +319,7 @@
291 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 319 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
292 reg = <0xfffc6000 0x18>; 320 reg = <0xfffc6000 0x18>;
293 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 321 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
294 #address-cells = <1>; 323 #address-cells = <1>;
295 #size-cells = <0>; 324 #size-cells = <0>;
296 status = "disabled"; 325 status = "disabled";