diff options
| author | Marek Vasut <marex@denx.de> | 2013-11-16 20:19:39 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-02-09 08:32:44 -0500 |
| commit | 19b529e9d2c7091ec690e9536bafb36a26439272 (patch) | |
| tree | 2d8cd070fff8c69f7bf32d0e2117036df20ebd0a /arch/arm/boot/dts | |
| parent | 6650d6db71ddbb1e321fbf4fb15c13e3e5f5e59b (diff) | |
ARM: dts: imx53: Fix display pinmux for M53EVK
Use the DISP1 pinmux on M53EVK for the LCD, not the LVDS.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/imx53-m53evk.dts | 46 |
1 files changed, 34 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index f3f02b5bfff2..08984c053c8a 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | crtcs = <&ipu 1>; | 26 | crtcs = <&ipu 1>; |
| 27 | interface-pix-fmt = "bgr666"; | 27 | interface-pix-fmt = "bgr666"; |
| 28 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&pinctrl_ipu_disp2>; | 29 | pinctrl-0 = <&pinctrl_ipu_disp1>; |
| 30 | 30 | ||
| 31 | display-timings { | 31 | display-timings { |
| 32 | 800x480p60 { | 32 | 800x480p60 { |
| @@ -292,18 +292,40 @@ | |||
| 292 | >; | 292 | >; |
| 293 | }; | 293 | }; |
| 294 | 294 | ||
| 295 | pinctrl_ipu_disp2: ipudisp2grp { | 295 | pinctrl_ipu_disp1: ipudisp1grp { |
| 296 | fsl,pins = < | 296 | fsl,pins = < |
| 297 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | 297 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 |
| 298 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | 298 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 |
| 299 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | 299 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 |
| 300 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | 300 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 |
| 301 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | 301 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 |
| 302 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | 302 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 |
| 303 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | 303 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 |
| 304 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | 304 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 |
| 305 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | 305 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 |
| 306 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | 306 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 |
| 307 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | ||
| 308 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | ||
| 309 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | ||
| 310 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | ||
| 311 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | ||
| 312 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | ||
| 313 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | ||
| 314 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | ||
| 315 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | ||
| 316 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | ||
| 317 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | ||
| 318 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | ||
| 319 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | ||
| 320 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | ||
| 321 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | ||
| 322 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | ||
| 323 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | ||
| 324 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | ||
| 325 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | ||
| 326 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | ||
| 327 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | ||
| 328 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | ||
| 307 | >; | 329 | >; |
| 308 | }; | 330 | }; |
| 309 | 331 | ||