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authorAndreas Färber <afaerber@suse.de>2014-07-25 07:12:31 -0400
committerMichal Simek <michal.simek@xilinx.com>2014-07-28 05:09:23 -0400
commitf07ab7a0f36a3cfcd675bf120156e36cf66d9583 (patch)
tree411ff4466d5f893d0f45147eb0470c245ec480b4 /arch/arm/boot/dts/zynq-7000.dtsi
parentfbb4add88c7d1240c75129c1442ec8dbed3182ae (diff)
ARM: dts: zynq: Add SPI
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index cf0f3e4057cf..ef11dab30446 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -140,6 +140,30 @@
140 interrupts = <0 50 4>; 140 interrupts = <0 50 4>;
141 }; 141 };
142 142
143 spi0: spi@e0006000 {
144 compatible = "xlnx,zynq-spi-r1p6";
145 reg = <0xe0006000 0x1000>;
146 status = "disabled";
147 interrupt-parent = <&intc>;
148 interrupts = <0 26 4>;
149 clocks = <&clkc 25>, <&clkc 34>;
150 clock-names = "ref_clk", "pclk";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154
155 spi1: spi@e0007000 {
156 compatible = "xlnx,zynq-spi-r1p6";
157 reg = <0xe0007000 0x1000>;
158 status = "disabled";
159 interrupt-parent = <&intc>;
160 interrupts = <0 49 4>;
161 clocks = <&clkc 26>, <&clkc 35>;
162 clock-names = "ref_clk", "pclk";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
143 gem0: ethernet@e000b000 { 167 gem0: ethernet@e000b000 {
144 compatible = "cdns,gem"; 168 compatible = "cdns,gem";
145 reg = <0xe000b000 0x4000>; 169 reg = <0xe000b000 0x4000>;