ARM: zynq: DT: Migrate UART to Cadence binding

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 760bbc463c5b..029cbac30454 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -105,19 +105,19 @@
                 };
 
                 uart0: serial@e0000000 {
-                        compatible = "xlnx,xuartps";
+                        compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                         status = "disabled";
                         clocks = <&clkc 23>, <&clkc 40>;
-                        clock-names = "ref_clk", "aper_clk";
+                        clock-names = "uart_clk", "pclk";
                         reg = <0xE0000000 0x1000>;
                         interrupts = <0 27 4>;
                 };
 
                 uart1: serial@e0001000 {
-                        compatible = "xlnx,xuartps";
+                        compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                         status = "disabled";
                         clocks = <&clkc 24>, <&clkc 41>;
-                        clock-names = "ref_clk", "aper_clk";
+                        clock-names = "uart_clk", "pclk";
                         reg = <0xE0001000 0x1000>;
                         interrupts = <0 50 4>;
                 };