diff options
| author | Peter Crosthwaite <crosthwaitepeter@gmail.com> | 2014-11-30 19:25:49 -0500 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-12-01 03:22:50 -0500 |
| commit | 8c7634c0ee4e2b62a361cc0285418e201d162f37 (patch) | |
| tree | 32c12892e63dc8d908fca8247e3dabff103a4dec /arch/arm/boot/dts/zynq-7000.dtsi | |
| parent | d86e3104e8066a5412ad3f9790592477a947a77e (diff) | |
arm: dts: zynq: Move crystal freq. to board level
The fact that all supported boards use the same 33MHz crystal is a
co-incidence. The Zynq PS support a range of crystal freqs so the
hardcoded setting should be removed from the dtsi. Re-implement it
on the board level.
This prepares support for Zynq boards with different crystal
frequencies (e.g. the Digilent ZYBO).
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 24036c440440..f8e4a28adfc0 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -244,7 +244,6 @@ | |||
| 244 | clkc: clkc@100 { | 244 | clkc: clkc@100 { |
| 245 | #clock-cells = <1>; | 245 | #clock-cells = <1>; |
| 246 | compatible = "xlnx,ps7-clkc"; | 246 | compatible = "xlnx,ps7-clkc"; |
| 247 | ps-clk-frequency = <33333333>; | ||
| 248 | fclk-enable = <0>; | 247 | fclk-enable = <0>; |
| 249 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | 248 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", |
| 250 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | 249 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", |