ARM: sunxi: dt: Add sample and output mmc clocks

Add the sample and output clocks for the MMC phase support.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>

1 files changed, 52 insertions, 20 deletions

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 62d932e9b7d1..3e7db5191516 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -241,35 +241,43 @@
                 };
 
                 mmc0_clk: clk@01c20088 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20088 0x4>;
                         clocks = <&osc24M>, <&pll6 0>;
-                        clock-output-names = "mmc0";
+                        clock-output-names = "mmc0",
+                                             "mmc0_output",
+                                             "mmc0_sample";
                 };
 
                 mmc1_clk: clk@01c2008c {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c2008c 0x4>;
                         clocks = <&osc24M>, <&pll6 0>;
-                        clock-output-names = "mmc1";
+                        clock-output-names = "mmc1",
+                                             "mmc1_output",
+                                             "mmc1_sample";
                 };
 
                 mmc2_clk: clk@01c20090 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20090 0x4>;
                         clocks = <&osc24M>, <&pll6 0>;
-                        clock-output-names = "mmc2";
+                        clock-output-names = "mmc2",
+                                             "mmc2_output",
+                                             "mmc2_sample";
                 };
 
                 mmc3_clk: clk@01c20094 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20094 0x4>;
                         clocks = <&osc24M>, <&pll6 0>;
-                        clock-output-names = "mmc3";
+                        clock-output-names = "mmc3",
+                                             "mmc3_output",
+                                             "mmc3_sample";
                 };
 
                 spi0_clk: clk@01c200a0 {
@@ -366,8 +374,14 @@
                 mmc0: mmc@01c0f000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c0f000 0x1000>;
-                        clocks = <&ahb1_gates 8>, <&mmc0_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 8>,
+                                 <&mmc0_clk 0>,
+                                 <&mmc0_clk 1>,
+                                 <&mmc0_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 8>;
                         reset-names = "ahb";
                         interrupts = <0 60 4>;
@@ -377,8 +391,14 @@
                 mmc1: mmc@01c10000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c10000 0x1000>;
-                        clocks = <&ahb1_gates 9>, <&mmc1_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 9>,
+                                 <&mmc1_clk 0>,
+                                 <&mmc1_clk 1>,
+                                 <&mmc1_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 9>;
                         reset-names = "ahb";
                         interrupts = <0 61 4>;
@@ -388,8 +408,14 @@
                 mmc2: mmc@01c11000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c11000 0x1000>;
-                        clocks = <&ahb1_gates 10>, <&mmc2_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 10>,
+                                 <&mmc2_clk 0>,
+                                 <&mmc2_clk 1>,
+                                 <&mmc2_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 10>;
                         reset-names = "ahb";
                         interrupts = <0 62 4>;
@@ -399,8 +425,14 @@
                 mmc3: mmc@01c12000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c12000 0x1000>;
-                        clocks = <&ahb1_gates 11>, <&mmc3_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 11>,
+                                 <&mmc3_clk 0>,
+                                 <&mmc3_clk 1>,
+                                 <&mmc3_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 11>;
                         reset-names = "ahb";
                         interrupts = <0 63 4>;