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authorLinus Walleij <linus.walleij@linaro.org>2014-02-03 08:32:20 -0500
committerLinus Walleij <linus.walleij@linaro.org>2014-02-04 14:46:50 -0500
commit8320062928161911bc46b0340e5a7cc0b3e3bb8e (patch)
tree99b2861896a9068f41a3aeb15105f772c0d3969c /arch/arm/boot/dts/ste-href-ab8500.dtsi
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
ARM: ux500: move AB8500 GPIOs to device tree
Move the AB8500 muxing and biasing settings over from the board file to the device tree, include it in the reference designs using the AB8500: HREF prior to v60, v60plus and Snowball. Set up these GPIO lines using hogs, just like in the board file. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-href-ab8500.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-href-ab8500.dtsi253
1 files changed, 253 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
new file mode 100644
index 000000000000..58b00d0f023e
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -0,0 +1,253 @@
1/*
2 * Copyright 2014 Linaro Ltd.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 soc {
14 prcmu@80157000 {
15 ab8500 {
16 ab8500-gpio {
17 /* Hog a few default settings */
18 pinctrl-names = "default";
19 pinctrl-0 = <&gpio2_default_mode>,
20 <&gpio4_default_mode>,
21 <&gpio10_default_mode>,
22 <&gpio11_default_mode>,
23 <&gpio12_default_mode>,
24 <&gpio13_default_mode>,
25 <&gpio16_default_mode>,
26 <&gpio24_default_mode>,
27 <&gpio25_default_mode>,
28 <&gpio36_default_mode>,
29 <&gpio37_default_mode>,
30 <&gpio38_default_mode>,
31 <&gpio39_default_mode>,
32 <&gpio42_default_mode>,
33 <&gpio26_default_mode>,
34 <&gpio35_default_mode>;
35
36 /*
37 * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
38 * are muxed in as GPIO, and configured as INPUT PULL DOWN
39 */
40 gpio2 {
41 gpio2_default_mode: gpio2_default {
42 default_mux {
43 ste,function = "gpio";
44 ste,pins = "gpio2_a_1";
45 };
46 default_cfg {
47 ste,pins = "GPIO2_T9";
48 input-enable;
49 bias-pull-down;
50 };
51 };
52 };
53 gpio4 {
54 gpio4_default_mode: gpio4_default {
55 default_mux {
56 ste,function = "gpio";
57 ste,pins = "gpio4_a_1";
58 };
59 default_cfg {
60 ste,pins = "GPIO4_W2";
61 input-enable;
62 bias-pull-down;
63 };
64 };
65 };
66 gpio10 {
67 gpio10_default_mode: gpio10_default {
68 default_mux {
69 ste,function = "gpio";
70 ste,pins = "gpio10_d_1";
71 };
72 default_cfg {
73 ste,pins = "GPIO10_U17";
74 input-enable;
75 bias-pull-down;
76 };
77 };
78 };
79 gpio11 {
80 gpio11_default_mode: gpio11_default {
81 default_mux {
82 ste,function = "gpio";
83 ste,pins = "gpio11_d_1";
84 };
85 default_cfg {
86 ste,pins = "GPIO11_AA18";
87 input-enable;
88 bias-pull-down;
89 };
90 };
91 };
92 gpio12 {
93 gpio12_default_mode: gpio12_default {
94 default_mux {
95 ste,function = "gpio";
96 ste,pins = "gpio12_d_1";
97 };
98 default_cfg {
99 ste,pins = "GPIO12_U16";
100 input-enable;
101 bias-pull-down;
102 };
103 };
104 };
105 gpio13 {
106 gpio13_default_mode: gpio13_default {
107 default_mux {
108 ste,function = "gpio";
109 ste,pins = "gpio13_d_1";
110 };
111 default_cfg {
112 ste,pins = "GPIO13_W17";
113 input-enable;
114 bias-pull-down;
115 };
116 };
117 };
118 gpio16 {
119 gpio16_default_mode: gpio16_default {
120 default_mux {
121 ste,function = "gpio";
122 ste,pins = "gpio16_a_1";
123 };
124 default_cfg {
125 ste,pins = "GPIO16_F15";
126 input-enable;
127 bias-pull-down;
128 };
129 };
130 };
131 gpio24 {
132 gpio24_default_mode: gpio24_default {
133 default_mux {
134 ste,function = "gpio";
135 ste,pins = "gpio24_a_1";
136 };
137 default_cfg {
138 ste,pins = "GPIO24_T14";
139 input-enable;
140 bias-pull-down;
141 };
142 };
143 };
144 gpio25 {
145 gpio25_default_mode: gpio25_default {
146 default_mux {
147 ste,function = "gpio";
148 ste,pins = "gpio25_a_1";
149 };
150 default_cfg {
151 ste,pins = "GPIO25_R16";
152 input-enable;
153 bias-pull-down;
154 };
155 };
156 };
157 gpio36 {
158 gpio36_default_mode: gpio36_default {
159 default_mux {
160 ste,function = "gpio";
161 ste,pins = "gpio36_a_1";
162 };
163 default_cfg {
164 ste,pins = "GPIO36_A17";
165 input-enable;
166 bias-pull-down;
167 };
168 };
169 };
170 gpio37 {
171 gpio37_default_mode: gpio37_default {
172 default_mux {
173 ste,function = "gpio";
174 ste,pins = "gpio37_a_1";
175 };
176 default_cfg {
177 ste,pins = "GPIO37_E15";
178 input-enable;
179 bias-pull-down;
180 };
181 };
182 };
183 gpio38 {
184 gpio38_default_mode: gpio38_default {
185 default_mux {
186 ste,function = "gpio";
187 ste,pins = "gpio38_a_1";
188 };
189 default_cfg {
190 ste,pins = "GPIO38_C17";
191 input-enable;
192 bias-pull-down;
193 };
194 };
195 };
196 gpio39 {
197 gpio39_default_mode: gpio39_default {
198 default_mux {
199 ste,function = "gpio";
200 ste,pins = "gpio39_a_1";
201 };
202 default_cfg {
203 ste,pins = "GPIO39_E16";
204 input-enable;
205 bias-pull-down;
206 };
207 };
208 };
209 gpio42 {
210 gpio42_default_mode: gpio42_default {
211 default_mux {
212 ste,function = "gpio";
213 ste,pins = "gpio42_a_1";
214 };
215 default_cfg {
216 ste,pins = "GPIO42_U2";
217 input-enable;
218 bias-pull-down;
219 };
220 };
221 };
222 /*
223 * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW
224 */
225 gpio26 {
226 gpio26_default_mode: gpio26_default {
227 default_mux {
228 ste,function = "gpio";
229 ste,pins = "gpio26_d_1";
230 };
231 default_cfg {
232 ste,pins = "GPIO26_M16";
233 output-low;
234 };
235 };
236 };
237 gpio35 {
238 gpio35_default_mode: gpio35_default {
239 default_mux {
240 ste,function = "gpio";
241 ste,pins = "gpio35_d_1";
242 };
243 default_cfg {
244 ste,pins = "GPIO35_W15";
245 output-low;
246 };
247 };
248 };
249 };
250 };
251 };
252 };
253};