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authorJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>2014-10-14 04:16:37 -0400
committerHeiko Stuebner <heiko@sntech.de>2014-10-20 05:52:26 -0400
commit5fe62b83cfed00b10b70593e95ffbeadf77ece78 (patch)
treed823062b09b3883b09fa38dc6321ecbd1b3f2cb3 /arch/arm/boot/dts/rk3066a.dtsi
parentb3e3a7b25825407144a0178f291b20697f1537fb (diff)
ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188
Add the I2S/PCM controller nodes and pin controls for rk3066 and rk3188. Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3066a.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi81
1 files changed, 81 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 8b11fbd58071..0e99470db772 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -63,6 +63,51 @@
63 }; 63 };
64 }; 64 };
65 65
66 i2s0: i2s@10118000 {
67 compatible = "rockchip,rk3066-i2s";
68 reg = <0x10118000 0x2000>;
69 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&i2s0_bus>;
74 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
75 dma-names = "tx", "rx";
76 clock-names = "i2s_hclk", "i2s_clk";
77 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
78 status = "disabled";
79 };
80
81 i2s1: i2s@1011a000 {
82 compatible = "rockchip,rk3066-i2s";
83 reg = <0x1011a000 0x2000>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2s1_bus>;
89 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
90 dma-names = "tx", "rx";
91 clock-names = "i2s_hclk", "i2s_clk";
92 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
93 status = "disabled";
94 };
95
96 i2s2: i2s@1011c000 {
97 compatible = "rockchip,rk3066-i2s";
98 reg = <0x1011c000 0x2000>;
99 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
101 #size-cells = <0>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2s2_bus>;
104 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
105 dma-names = "tx", "rx";
106 clock-names = "i2s_hclk", "i2s_clk";
107 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
108 status = "disabled";
109 };
110
66 cru: clock-controller@20000000 { 111 cru: clock-controller@20000000 {
67 compatible = "rockchip,rk3066a-cru"; 112 compatible = "rockchip,rk3066a-cru";
68 reg = <0x20000000 0x1000>; 113 reg = <0x20000000 0x1000>;
@@ -415,6 +460,42 @@
415 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; 460 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
416 }; 461 };
417 }; 462 };
463
464 i2s0 {
465 i2s0_bus: i2s0-bus {
466 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
467 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
468 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
469 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
470 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
471 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
472 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
473 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
474 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
475 };
476 };
477
478 i2s1 {
479 i2s1_bus: i2s1-bus {
480 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
481 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
482 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
483 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
484 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
485 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
486 };
487 };
488
489 i2s2 {
490 i2s2_bus: i2s2-bus {
491 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
492 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
493 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
494 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
495 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
496 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
497 };
498 };
418 }; 499 };
419}; 500};
420 501