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authorHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>2014-12-09 20:21:12 -0500
committerSimon Horman <horms+renesas@verge.net.au>2014-12-21 05:07:19 -0500
commitbe16cd385c08dce7efa406704b5aa420ef6d1992 (patch)
tree2a666aa391cfcdbd5997da148ad5a1995f0914e5 /arch/arm/boot/dts/r8a7794.dtsi
parentce85ad47882fe375dcb3f7cce6c10ae800ac2d9c (diff)
ARM: shmobile: r8a7794: Add SYS-DMAC clocks to device tree
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> [horms: resolved conflicts] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r8a7794.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 13e4a8d73029..6d95638987e7 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -479,16 +479,19 @@
479 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 479 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
480 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 480 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
481 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 481 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
482 <&mp_clk>, <&mp_clk>, <&mp_clk>; 482 <&mp_clk>, <&mp_clk>, <&mp_clk>,
483 <&zs_clk>, <&zs_clk>;
483 #clock-cells = <1>; 484 #clock-cells = <1>;
484 clock-indices = < 485 clock-indices = <
485 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 486 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
486 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 487 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
487 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 488 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
489 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
488 >; 490 >;
489 clock-output-names = 491 clock-output-names =
490 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 492 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
491 "scifb1", "msiof1", "scifb2"; 493 "scifb1", "msiof1", "scifb2",
494 "sys-dmac1", "sys-dmac0";
492 }; 495 };
493 mstp3_clks: mstp3_clks@e615013c { 496 mstp3_clks: mstp3_clks@e615013c {
494 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 497 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";