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authorTao Huang <Tao.Huang@csr.com>2014-11-25 05:46:43 -0500
committerBarry Song <Baohua.Song@csr.com>2014-11-25 05:46:43 -0500
commit1f634d7415441f723791d822fcde12dd50838d51 (patch)
treef90676649d5b625a1bbafaffd2609987d86e3554 /arch/arm/boot/dts/prima2.dtsi
parent64a7507a7496f5adb88a55e572c659a82997f9c9 (diff)
ARM: dts: prima2: add resets property for GPS nodes
this patch adds missed resets property for CSR SiRFprimaII GPS related nodes. Signed-off-by: Tao Huang <Tao.Huang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com>
Diffstat (limited to 'arch/arm/boot/dts/prima2.dtsi')
-rw-r--r--arch/arm/boot/dts/prima2.dtsi3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3bb1b4ab55de..70b2ad5d837e 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -178,6 +178,7 @@
178 compatible = "sirf,prima2-dspif"; 178 compatible = "sirf,prima2-dspif";
179 reg = <0xa8000000 0x10000>; 179 reg = <0xa8000000 0x10000>;
180 interrupts = <9>; 180 interrupts = <9>;
181 resets = <&rstc 1>;
181 }; 182 };
182 183
183 gps@a8010000 { 184 gps@a8010000 {
@@ -185,6 +186,7 @@
185 reg = <0xa8010000 0x10000>; 186 reg = <0xa8010000 0x10000>;
186 interrupts = <7>; 187 interrupts = <7>;
187 clocks = <&clks 9>; 188 clocks = <&clks 9>;
189 resets = <&rstc 2>;
188 }; 190 };
189 191
190 dsp@a9000000 { 192 dsp@a9000000 {
@@ -192,6 +194,7 @@
192 reg = <0xa9000000 0x1000000>; 194 reg = <0xa9000000 0x1000000>;
193 interrupts = <8>; 195 interrupts = <8>;
194 clocks = <&clks 8>; 196 clocks = <&clks 8>;
197 resets = <&rstc 0>;
195 }; 198 };
196 }; 199 };
197 200