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authorTony Lindgren <tony@atomide.com>2014-09-18 12:03:36 -0400
committerTony Lindgren <tony@atomide.com>2014-09-18 12:03:36 -0400
commit271d4c6bc709d922e5f8913bcb64d6c53a752e31 (patch)
treea3deef7d05862e062d69bba8a043a126b13f7ee3 /arch/arm/boot/dts/omap3-n900.dts
parenta4ff93c185787412936bc8414f14f50bdd56e546 (diff)
ARM: dts: Add support for Ethernet on some N900 macro boards
As we have support for this in board-rx51-peripherals.c, let's add it to the .dts files too. Note that the reset GPIO will eventually go to the driver. For now let's just pull it down and skip any further reset in case the bootloader has configured the MAC address so NFSroot works. Also note that after 3430-sdp are using proper GPMC timings we can remove the tests for smsc,lan91c94 in gpmc.c. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3-n900.dts')
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts42
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index f0d82369ef13..19a585773abe 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -134,6 +134,14 @@
134 >; 134 >;
135 }; 135 };
136 136
137 ethernet_pins: pinmux_ethernet_pins {
138 pinctrl-single,pins = <
139 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
140 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
141 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
142 >;
143 };
144
137 i2c1_pins: pinmux_i2c1_pins { 145 i2c1_pins: pinmux_i2c1_pins {
138 pinctrl-single,pins = < 146 pinctrl-single,pins = <
139 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 147 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
@@ -578,6 +586,8 @@
578 586
579&gpmc { 587&gpmc {
580 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ 588 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
589 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
590 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
581 591
582 /* gpio-irq for dma: 65 */ 592 /* gpio-irq for dma: 65 */
583 593
@@ -646,6 +656,38 @@
646 reg = <0x004c0000 0x0fb40000>; 656 reg = <0x004c0000 0x0fb40000>;
647 }; 657 };
648 }; 658 };
659
660 ethernet@gpmc {
661 compatible = "smsc,lan91c94";
662 interrupt-parent = <&gpio2>;
663 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
664 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
665 bank-width = <2>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&ethernet_pins>;
668 gpmc,device-width = <2>;
669 gpmc,sync-clk-ps = <0>;
670 gpmc,cs-on-ns = <0>;
671 gpmc,cs-rd-off-ns = <48>;
672 gpmc,cs-wr-off-ns = <24>;
673 gpmc,adv-on-ns = <0>;
674 gpmc,adv-rd-off-ns = <0>;
675 gpmc,adv-wr-off-ns = <0>;
676 gpmc,we-on-ns = <12>;
677 gpmc,we-off-ns = <18>;
678 gpmc,oe-on-ns = <12>;
679 gpmc,oe-off-ns = <48>;
680 gpmc,page-burst-access-ns = <0>;
681 gpmc,access-ns = <42>;
682 gpmc,rd-cycle-ns = <180>;
683 gpmc,wr-cycle-ns = <180>;
684 gpmc,bus-turnaround-ns = <0>;
685 gpmc,cycle2cycle-delay-ns = <0>;
686 gpmc,wait-monitoring-ns = <0>;
687 gpmc,clk-activation-ns = <0>;
688 gpmc,wr-access-ns = <0>;
689 gpmc,wr-data-mux-bus-ns = <12>;
690 };
649}; 691};
650 692
651&mcspi1 { 693&mcspi1 {