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authorMarek Belisko <marek@goldelico.com>2014-10-17 16:32:03 -0400
committerTony Lindgren <tony@atomide.com>2014-11-10 17:27:35 -0500
commit021fe93645bbabeabd91a232ba24b984c215b199 (patch)
tree38a6d07a326854ce09c5d76cef9fec1a0dfdd3fb /arch/arm/boot/dts/omap3-gta04.dtsi
parente5ee042b67cc687693b6b8e23aa25b5a311b860f (diff)
ARM: dts: omap3-gta04: Use omap specific pinctrl defines
Use omap specific pinctrl defines (OMAP3_CORE1_IOPAD) to configure the padconf register offset. Signed-off-by: Marek Belisko <marek@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3-gta04.dtsi')
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi82
1 files changed, 41 insertions, 41 deletions
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index 91bba857e0f9..655d6e920a86 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -104,67 +104,67 @@
104 104
105 uart1_pins: pinmux_uart1_pins { 105 uart1_pins: pinmux_uart1_pins {
106 pinctrl-single,pins = < 106 pinctrl-single,pins = <
107 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 107 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
108 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ 108 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
109 >; 109 >;
110 }; 110 };
111 111
112 uart2_pins: pinmux_uart2_pins { 112 uart2_pins: pinmux_uart2_pins {
113 pinctrl-single,pins = < 113 pinctrl-single,pins = <
114 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 114 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
115 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 115 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
116 >; 116 >;
117 }; 117 };
118 118
119 uart3_pins: pinmux_uart3_pins { 119 uart3_pins: pinmux_uart3_pins {
120 pinctrl-single,pins = < 120 pinctrl-single,pins = <
121 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 121 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
122 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ 122 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
123 >; 123 >;
124 }; 124 };
125 125
126 mmc1_pins: pinmux_mmc1_pins { 126 mmc1_pins: pinmux_mmc1_pins {
127 pinctrl-single,pins = < 127 pinctrl-single,pins = <
128 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 128 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
129 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 129 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
130 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 130 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
131 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 131 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
132 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 132 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
133 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 133 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
134 >; 134 >;
135 }; 135 };
136 136
137 dss_dpi_pins: pinmux_dss_dpi_pins { 137 dss_dpi_pins: pinmux_dss_dpi_pins {
138 pinctrl-single,pins = < 138 pinctrl-single,pins = <
139 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 139 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
140 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 140 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
141 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 141 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
142 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 142 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
143 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 143 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
144 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 144 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
145 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 145 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
146 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 146 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
147 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 147 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
148 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 148 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
149 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 149 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
150 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 150 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
151 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 151 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
152 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 152 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
153 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 153 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
154 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 154 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
155 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 155 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
156 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 156 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
157 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 157 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
158 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 158 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
159 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 159 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
160 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 160 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
161 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 161 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
162 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 162 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
163 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 163 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
164 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 164 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
165 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 165 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
166 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 166 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
167 >; 167 >;
168 }; 168 };
169}; 169};
170 170
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