diff options
| author | Dmitry Lifshitz <lifshitz@compulab.co.il> | 2014-01-12 08:22:44 -0500 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-02-28 17:09:07 -0500 |
| commit | fb5f895fd303b2609a78bf553c954e1df1d6d16d (patch) | |
| tree | 0bfa9b0b9f831b38b47f3220b7caff0912a18d34 /arch/arm/boot/dts/omap3-cm-t3730.dts | |
| parent | 3a24a3cb1752b265cc5feb92a5fed987443c078b (diff) | |
ARM: dts: sbc-t3x: use omap specific pinctrl defines
Use omap specific pinctrl defines (OMAP3_CORE1_IOPAD) to configure
the padconf register offset.
This simplify further support of CompuLab's boards based on omap36xx,
omap34xx and am35x.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3-cm-t3730.dts')
| -rw-r--r-- | arch/arm/boot/dts/omap3-cm-t3730.dts | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 486f4d6c4219..508cd9b413fb 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts | |||
| @@ -34,44 +34,44 @@ | |||
| 34 | &omap3_pmx_core { | 34 | &omap3_pmx_core { |
| 35 | mmc1_pins: pinmux_mmc1_pins { | 35 | mmc1_pins: pinmux_mmc1_pins { |
| 36 | pinctrl-single,pins = < | 36 | pinctrl-single,pins = < |
| 37 | 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | 37 | OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0)/* sdmmc1_clk.sdmmc1_clk */ |
| 38 | 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | 38 | OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ |
| 39 | 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | 39 | OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ |
| 40 | 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | 40 | OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ |
| 41 | 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | 41 | OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ |
| 42 | 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | 42 | OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ |
| 43 | >; | 43 | >; |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | mmc2_pins: pinmux_mmc2_pins { | 46 | mmc2_pins: pinmux_mmc2_pins { |
| 47 | pinctrl-single,pins = < | 47 | pinctrl-single,pins = < |
| 48 | 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ | 48 | OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ |
| 49 | 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ | 49 | OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ |
| 50 | 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ | 50 | OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ |
| 51 | 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ | 51 | OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ |
| 52 | 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ | 52 | OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ |
| 53 | 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ | 53 | OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ |
| 54 | >; | 54 | >; |
| 55 | }; | 55 | }; |
| 56 | 56 | ||
| 57 | smsc1_pins: pinmux_smsc1_pins { | 57 | smsc1_pins: pinmux_smsc1_pins { |
| 58 | pinctrl-single,pins = < | 58 | pinctrl-single,pins = < |
| 59 | 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ | 59 | OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ |
| 60 | 0x16a (PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ | 60 | OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ |
| 61 | >; | 61 | >; |
| 62 | }; | 62 | }; |
| 63 | 63 | ||
| 64 | uart3_pins: pinmux_uart3_pins { | 64 | uart3_pins: pinmux_uart3_pins { |
| 65 | pinctrl-single,pins = < | 65 | pinctrl-single,pins = < |
| 66 | 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | 66 | OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ |
| 67 | 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | 67 | OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ |
| 68 | >; | 68 | >; |
| 69 | }; | 69 | }; |
| 70 | 70 | ||
| 71 | wl12xx_gpio: pinmux_wl12xx_gpio { | 71 | wl12xx_gpio: pinmux_wl12xx_gpio { |
| 72 | pinctrl-single,pins = < | 72 | pinctrl-single,pins = < |
| 73 | 0xb2 (PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ | 73 | OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ |
| 74 | 0x134 (PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ | 74 | OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ |
| 75 | >; | 75 | >; |
| 76 | }; | 76 | }; |
| 77 | }; | 77 | }; |