diff options
| author | Ezequiel Garcia <ezequiel.garcia@free-electrons.com> | 2013-07-26 09:18:05 -0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-08-06 10:11:53 -0400 |
| commit | 54397d85349f5b5c5f11f5eef431f9e86a338d16 (patch) | |
| tree | ac8bfe42574180161d1860f256dc8bbf648d92fd /arch/arm/boot/dts/kirkwood-6282.dtsi | |
| parent | 3ec81e7e0374734893941258c8cbb998a780c5eb (diff) | |
ARM: kirkwood: Relocate PCIe device tree nodes
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of the ocp node, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to
correspond to each MBus window.
In addition, we encode the PCIe memory and I/O apertures in the MBus
node, according to the MBus DT binding specification. The choice made
is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for
I/O space. These apertures can be changed in each per-board DT file.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/kirkwood-6282.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/kirkwood-6282.dtsi | 102 |
1 files changed, 55 insertions, 47 deletions
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index a63a11137262..3933a331ddc2 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi | |||
| @@ -1,4 +1,59 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | ||
| 3 | pcie-controller { | ||
| 4 | compatible = "marvell,kirkwood-pcie"; | ||
| 5 | status = "disabled"; | ||
| 6 | device_type = "pci"; | ||
| 7 | |||
| 8 | #address-cells = <3>; | ||
| 9 | #size-cells = <2>; | ||
| 10 | |||
| 11 | bus-range = <0x00 0xff>; | ||
| 12 | |||
| 13 | ranges = | ||
| 14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 15 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | ||
| 16 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | ||
| 17 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 18 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | ||
| 19 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ | ||
| 20 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; | ||
| 21 | |||
| 22 | pcie@1,0 { | ||
| 23 | device_type = "pci"; | ||
| 24 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 25 | reg = <0x0800 0 0 0 0>; | ||
| 26 | #address-cells = <3>; | ||
| 27 | #size-cells = <2>; | ||
| 28 | #interrupt-cells = <1>; | ||
| 29 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 30 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 31 | interrupt-map-mask = <0 0 0 0>; | ||
| 32 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 33 | marvell,pcie-port = <0>; | ||
| 34 | marvell,pcie-lane = <0>; | ||
| 35 | clocks = <&gate_clk 2>; | ||
| 36 | status = "disabled"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | pcie@2,0 { | ||
| 40 | device_type = "pci"; | ||
| 41 | assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; | ||
| 42 | reg = <0x1000 0 0 0 0>; | ||
| 43 | #address-cells = <3>; | ||
| 44 | #size-cells = <2>; | ||
| 45 | #interrupt-cells = <1>; | ||
| 46 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 47 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 48 | interrupt-map-mask = <0 0 0 0>; | ||
| 49 | interrupt-map = <0 0 0 0 &intc 10>; | ||
| 50 | marvell,pcie-port = <1>; | ||
| 51 | marvell,pcie-lane = <0>; | ||
| 52 | clocks = <&gate_clk 18>; | ||
| 53 | status = "disabled"; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | }; | ||
| 2 | ocp@f1000000 { | 57 | ocp@f1000000 { |
| 3 | 58 | ||
| 4 | pinctrl: pinctrl@10000 { | 59 | pinctrl: pinctrl@10000 { |
| @@ -94,52 +149,5 @@ | |||
| 94 | status = "disabled"; | 149 | status = "disabled"; |
| 95 | }; | 150 | }; |
| 96 | 151 | ||
| 97 | pcie-controller { | ||
| 98 | compatible = "marvell,kirkwood-pcie"; | ||
| 99 | status = "disabled"; | ||
| 100 | device_type = "pci"; | ||
| 101 | |||
| 102 | #address-cells = <3>; | ||
| 103 | #size-cells = <2>; | ||
| 104 | |||
| 105 | bus-range = <0x00 0xff>; | ||
| 106 | |||
| 107 | ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 108 | 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ | ||
| 109 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 110 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 111 | |||
| 112 | pcie@1,0 { | ||
| 113 | device_type = "pci"; | ||
| 114 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 115 | reg = <0x0800 0 0 0 0>; | ||
| 116 | #address-cells = <3>; | ||
| 117 | #size-cells = <2>; | ||
| 118 | #interrupt-cells = <1>; | ||
| 119 | ranges; | ||
| 120 | interrupt-map-mask = <0 0 0 0>; | ||
| 121 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 122 | marvell,pcie-port = <0>; | ||
| 123 | marvell,pcie-lane = <0>; | ||
| 124 | clocks = <&gate_clk 2>; | ||
| 125 | status = "disabled"; | ||
| 126 | }; | ||
| 127 | |||
| 128 | pcie@2,0 { | ||
| 129 | device_type = "pci"; | ||
| 130 | assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; | ||
| 131 | reg = <0x1000 0 0 0 0>; | ||
| 132 | #address-cells = <3>; | ||
| 133 | #size-cells = <2>; | ||
| 134 | #interrupt-cells = <1>; | ||
| 135 | ranges; | ||
| 136 | interrupt-map-mask = <0 0 0 0>; | ||
| 137 | interrupt-map = <0 0 0 0 &intc 10>; | ||
| 138 | marvell,pcie-port = <1>; | ||
| 139 | marvell,pcie-lane = <0>; | ||
| 140 | clocks = <&gate_clk 18>; | ||
| 141 | status = "disabled"; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | }; | 152 | }; |
| 145 | }; | 153 | }; |