aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx6sx.dtsi
diff options
context:
space:
mode:
authorShawn Guo <shawn.guo@freescale.com>2014-05-13 08:21:35 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-07-18 04:49:30 -0400
commitb1d17f68e5c5ffe131c53be792f03996430d86cd (patch)
treebffc259c5d5c76da32c359eefddc3701accaa887 /arch/arm/boot/dts/imx6sx.dtsi
parent743636f25f1da95d05483d8b986dc6a4166fed91 (diff)
ARM: dts: imx: add initial imx6sx device tree source
Add initial device tree source for i.MX6 SoloX SoC. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi1202
1 files changed, 1202 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
new file mode 100644
index 000000000000..ac3866c80727
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -0,0 +1,1202 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6sx-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
17 can0 = &flexcan1;
18 can1 = &flexcan2;
19 ethernet0 = &fec1;
20 ethernet1 = &fec2;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 mmc3 = &usdhc4;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 serial5 = &uart6;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
46 spi4 = &ecspi5;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu0: cpu@0 {
56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
58 reg = <0>;
59 next-level-cache = <&L2>;
60 operating-points = <
61 /* kHz uV */
62 996000 1250000
63 792000 1175000
64 396000 1075000
65 >;
66 fsl,soc-operating-points = <
67 /* ARM kHz SOC uV */
68 996000 1175000
69 792000 1175000
70 396000 1175000
71 >;
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <&reg_arm>;
81 soc-supply = <&reg_soc>;
82 };
83 };
84
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 interrupt-controller;
89 reg = <0x00a01000 0x1000>,
90 <0x00a00100 0x100>;
91 };
92
93 clocks {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 ckil: clock@0 {
98 compatible = "fixed-clock";
99 reg = <0>;
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 #clock-cells = <0>;
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
111 };
112
113 ipp_di0: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
119 };
120
121 ipp_di1: clock@3 {
122 compatible = "fixed-clock";
123 reg = <3>;
124 #clock-cells = <0>;
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
127 };
128 };
129
130 soc {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
135 ranges;
136
137 pmu {
138 compatible = "arm,cortex-a9-pmu";
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
140 };
141
142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
146 };
147
148 L2: l2-cache@00a02000 {
149 compatible = "arm,pl310-cache";
150 reg = <0x00a02000 0x1000>;
151 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
152 cache-unified;
153 cache-level = <2>;
154 arm,tag-latency = <4 2 3>;
155 arm,data-latency = <4 2 3>;
156 };
157
158 dma_apbh: dma-apbh@01804000 {
159 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x01804000 0x2000>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
166 #dma-cells = <1>;
167 dma-channels = <4>;
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
169 };
170
171 gpmi: gpmi-nand@01806000{
172 compatible = "fsl,imx6sx-gpmi-nand";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
182 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
183 <&clks IMX6SX_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
187 dma-names = "rx-tx";
188 status = "disabled";
189 };
190
191 aips1: aips-bus@02000000 {
192 compatible = "fsl,aips-bus", "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 reg = <0x02000000 0x100000>;
196 ranges;
197
198 spba-bus@02000000 {
199 compatible = "fsl,spba-bus", "simple-bus";
200 #address-cells = <1>;
201 #size-cells = <1>;
202 reg = <0x02000000 0x40000>;
203 ranges;
204
205 spdif: spdif@02004000 {
206 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
207 reg = <0x02004000 0x4000>;
208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209 dmas = <&sdma 14 18 0>,
210 <&sdma 15 18 0>;
211 dma-names = "rx", "tx";
212 clocks = <&clks IMX6SX_CLK_SPDIF>,
213 <&clks IMX6SX_CLK_OSC>,
214 <&clks IMX6SX_CLK_SPDIF>,
215 <&clks 0>, <&clks 0>, <&clks 0>,
216 <&clks IMX6SX_CLK_IPG>,
217 <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_SPBA>;
219 clock-names = "core", "rxtx0",
220 "rxtx1", "rxtx2",
221 "rxtx3", "rxtx4",
222 "rxtx5", "rxtx6",
223 "rxtx7", "dma";
224 status = "disabled";
225 };
226
227 ecspi1: ecspi@02008000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02008000 0x4000>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SX_CLK_ECSPI1>,
234 <&clks IMX6SX_CLK_ECSPI1>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
238
239 ecspi2: ecspi@0200c000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
243 reg = <0x0200c000 0x4000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6SX_CLK_ECSPI2>,
246 <&clks IMX6SX_CLK_ECSPI2>;
247 clock-names = "ipg", "per";
248 status = "disabled";
249 };
250
251 ecspi3: ecspi@02010000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02010000 0x4000>;
256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI3>,
258 <&clks IMX6SX_CLK_ECSPI3>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 ecspi4: ecspi@02014000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI4>,
270 <&clks IMX6SX_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
274
275 uart1: serial@02020000 {
276 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
277 reg = <0x02020000 0x4000>;
278 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SX_CLK_UART_IPG>,
280 <&clks IMX6SX_CLK_UART_SERIAL>;
281 clock-names = "ipg", "per";
282 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
283 dma-names = "rx", "tx";
284 status = "disabled";
285 };
286
287 esai: esai@02024000 {
288 reg = <0x02024000 0x4000>;
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
291 <&clks IMX6SX_CLK_ESAI_MEM>,
292 <&clks IMX6SX_CLK_ESAI_EXTAL>,
293 <&clks IMX6SX_CLK_ESAI_IPG>,
294 <&clks IMX6SX_CLK_SPBA>;
295 clock-names = "core", "mem", "extal",
296 "fsys", "dma";
297 status = "disabled";
298 };
299
300 ssi1: ssi@02028000 {
301 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
305 <&clks IMX6SX_CLK_SSI1>;
306 clock-names = "ipg", "baud";
307 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
308 dma-names = "rx", "tx";
309 status = "disabled";
310 };
311
312 ssi2: ssi@0202c000 {
313 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
314 reg = <0x0202c000 0x4000>;
315 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
317 <&clks IMX6SX_CLK_SSI2>;
318 clock-names = "ipg", "baud";
319 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
320 dma-names = "rx", "tx";
321 status = "disabled";
322 };
323
324 ssi3: ssi@02030000 {
325 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
326 reg = <0x02030000 0x4000>;
327 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
329 <&clks IMX6SX_CLK_SSI3>;
330 clock-names = "ipg", "baud";
331 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
332 dma-names = "rx", "tx";
333 status = "disabled";
334 };
335
336 asrc: asrc@02034000 {
337 reg = <0x02034000 0x4000>;
338 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
340 <&clks IMX6SX_CLK_ASRC_IPG>,
341 <&clks IMX6SX_CLK_SPDIF>,
342 <&clks IMX6SX_CLK_SPBA>;
343 clock-names = "mem", "ipg", "asrck", "dma";
344 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
345 <&sdma 19 20 1>, <&sdma 20 20 1>,
346 <&sdma 21 20 1>, <&sdma 22 20 1>;
347 dma-names = "rxa", "rxb", "rxc",
348 "txa", "txb", "txc";
349 status = "okay";
350 };
351 };
352
353 pwm1: pwm@02080000 {
354 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
355 reg = <0x02080000 0x4000>;
356 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6SX_CLK_PWM1>,
358 <&clks IMX6SX_CLK_PWM1>;
359 clock-names = "ipg", "per";
360 #pwm-cells = <2>;
361 };
362
363 pwm2: pwm@02084000 {
364 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
365 reg = <0x02084000 0x4000>;
366 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6SX_CLK_PWM2>,
368 <&clks IMX6SX_CLK_PWM2>;
369 clock-names = "ipg", "per";
370 #pwm-cells = <2>;
371 };
372
373 pwm3: pwm@02088000 {
374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
375 reg = <0x02088000 0x4000>;
376 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6SX_CLK_PWM3>,
378 <&clks IMX6SX_CLK_PWM3>;
379 clock-names = "ipg", "per";
380 #pwm-cells = <2>;
381 };
382
383 pwm4: pwm@0208c000 {
384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
385 reg = <0x0208c000 0x4000>;
386 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6SX_CLK_PWM4>,
388 <&clks IMX6SX_CLK_PWM4>;
389 clock-names = "ipg", "per";
390 #pwm-cells = <2>;
391 };
392
393 flexcan1: can@02090000 {
394 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
395 reg = <0x02090000 0x4000>;
396 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
398 <&clks IMX6SX_CLK_CAN1_SERIAL>;
399 clock-names = "ipg", "per";
400 status = "disabled";
401 };
402
403 flexcan2: can@02094000 {
404 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
405 reg = <0x02094000 0x4000>;
406 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
408 <&clks IMX6SX_CLK_CAN2_SERIAL>;
409 clock-names = "ipg", "per";
410 status = "disabled";
411 };
412
413 gpt: gpt@02098000 {
414 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
415 reg = <0x02098000 0x4000>;
416 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
418 <&clks IMX6SX_CLK_GPT_SERIAL>;
419 clock-names = "ipg", "per";
420 };
421
422 gpio1: gpio@0209c000 {
423 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
424 reg = <0x0209c000 0x4000>;
425 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
427 gpio-controller;
428 #gpio-cells = <2>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 };
432
433 gpio2: gpio@020a0000 {
434 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
435 reg = <0x020a0000 0x4000>;
436 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
443
444 gpio3: gpio@020a4000 {
445 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
446 reg = <0x020a4000 0x4000>;
447 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
449 gpio-controller;
450 #gpio-cells = <2>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 };
454
455 gpio4: gpio@020a8000 {
456 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
457 reg = <0x020a8000 0x4000>;
458 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
460 gpio-controller;
461 #gpio-cells = <2>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 };
465
466 gpio5: gpio@020ac000 {
467 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
468 reg = <0x020ac000 0x4000>;
469 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
471 gpio-controller;
472 #gpio-cells = <2>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
475 };
476
477 gpio6: gpio@020b0000 {
478 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
479 reg = <0x020b0000 0x4000>;
480 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
482 gpio-controller;
483 #gpio-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 };
487
488 gpio7: gpio@020b4000 {
489 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
490 reg = <0x020b4000 0x4000>;
491 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
498
499 kpp: kpp@020b8000 {
500 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
501 reg = <0x020b8000 0x4000>;
502 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6SX_CLK_DUMMY>;
504 status = "disabled";
505 };
506
507 wdog1: wdog@020bc000 {
508 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
509 reg = <0x020bc000 0x4000>;
510 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clks IMX6SX_CLK_DUMMY>;
512 };
513
514 wdog2: wdog@020c0000 {
515 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
516 reg = <0x020c0000 0x4000>;
517 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6SX_CLK_DUMMY>;
519 status = "disabled";
520 };
521
522 clks: ccm@020c4000 {
523 compatible = "fsl,imx6sx-ccm";
524 reg = <0x020c4000 0x4000>;
525 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
527 #clock-cells = <1>;
528 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
529 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
530 };
531
532 anatop: anatop@020c8000 {
533 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
534 "syscon", "simple-bus";
535 reg = <0x020c8000 0x1000>;
536 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
539
540 regulator-1p1@110 {
541 compatible = "fsl,anatop-regulator";
542 regulator-name = "vdd1p1";
543 regulator-min-microvolt = <800000>;
544 regulator-max-microvolt = <1375000>;
545 regulator-always-on;
546 anatop-reg-offset = <0x110>;
547 anatop-vol-bit-shift = <8>;
548 anatop-vol-bit-width = <5>;
549 anatop-min-bit-val = <4>;
550 anatop-min-voltage = <800000>;
551 anatop-max-voltage = <1375000>;
552 };
553
554 regulator-3p0@120 {
555 compatible = "fsl,anatop-regulator";
556 regulator-name = "vdd3p0";
557 regulator-min-microvolt = <2800000>;
558 regulator-max-microvolt = <3150000>;
559 regulator-always-on;
560 anatop-reg-offset = <0x120>;
561 anatop-vol-bit-shift = <8>;
562 anatop-vol-bit-width = <5>;
563 anatop-min-bit-val = <0>;
564 anatop-min-voltage = <2625000>;
565 anatop-max-voltage = <3400000>;
566 };
567
568 regulator-2p5@130 {
569 compatible = "fsl,anatop-regulator";
570 regulator-name = "vdd2p5";
571 regulator-min-microvolt = <2100000>;
572 regulator-max-microvolt = <2875000>;
573 regulator-always-on;
574 anatop-reg-offset = <0x130>;
575 anatop-vol-bit-shift = <8>;
576 anatop-vol-bit-width = <5>;
577 anatop-min-bit-val = <0>;
578 anatop-min-voltage = <2100000>;
579 anatop-max-voltage = <2875000>;
580 };
581
582 reg_arm: regulator-vddcore@140 {
583 compatible = "fsl,anatop-regulator";
584 regulator-name = "cpu";
585 regulator-min-microvolt = <725000>;
586 regulator-max-microvolt = <1450000>;
587 regulator-always-on;
588 anatop-reg-offset = <0x140>;
589 anatop-vol-bit-shift = <0>;
590 anatop-vol-bit-width = <5>;
591 anatop-delay-reg-offset = <0x170>;
592 anatop-delay-bit-shift = <24>;
593 anatop-delay-bit-width = <2>;
594 anatop-min-bit-val = <1>;
595 anatop-min-voltage = <725000>;
596 anatop-max-voltage = <1450000>;
597 };
598
599 reg_pcie: regulator-vddpcie@140 {
600 compatible = "fsl,anatop-regulator";
601 regulator-name = "vddpcie";
602 regulator-min-microvolt = <725000>;
603 regulator-max-microvolt = <1450000>;
604 anatop-reg-offset = <0x140>;
605 anatop-vol-bit-shift = <9>;
606 anatop-vol-bit-width = <5>;
607 anatop-delay-reg-offset = <0x170>;
608 anatop-delay-bit-shift = <26>;
609 anatop-delay-bit-width = <2>;
610 anatop-min-bit-val = <1>;
611 anatop-min-voltage = <725000>;
612 anatop-max-voltage = <1450000>;
613 };
614
615 reg_soc: regulator-vddsoc@140 {
616 compatible = "fsl,anatop-regulator";
617 regulator-name = "vddsoc";
618 regulator-min-microvolt = <725000>;
619 regulator-max-microvolt = <1450000>;
620 regulator-always-on;
621 anatop-reg-offset = <0x140>;
622 anatop-vol-bit-shift = <18>;
623 anatop-vol-bit-width = <5>;
624 anatop-delay-reg-offset = <0x170>;
625 anatop-delay-bit-shift = <28>;
626 anatop-delay-bit-width = <2>;
627 anatop-min-bit-val = <1>;
628 anatop-min-voltage = <725000>;
629 anatop-max-voltage = <1450000>;
630 };
631 };
632
633 tempmon: tempmon {
634 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
635 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
636 fsl,tempmon = <&anatop>;
637 fsl,tempmon-data = <&ocotp>;
638 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
639 };
640
641 usbphy1: usbphy@020c9000 {
642 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
643 reg = <0x020c9000 0x1000>;
644 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clks IMX6SX_CLK_USBPHY1>;
646 fsl,anatop = <&anatop>;
647 };
648
649 usbphy2: usbphy@020ca000 {
650 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
651 reg = <0x020ca000 0x1000>;
652 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX6SX_CLK_USBPHY2>;
654 fsl,anatop = <&anatop>;
655 };
656
657 snvs: snvs@020cc000 {
658 compatible = "fsl,sec-v4.0-mon", "simple-bus";
659 #address-cells = <1>;
660 #size-cells = <1>;
661 ranges = <0 0x020cc000 0x4000>;
662
663 snvs-rtc-lp@34 {
664 compatible = "fsl,sec-v4.0-mon-rtc-lp";
665 reg = <0x34 0x58>;
666 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
667 };
668 };
669
670 epit1: epit@020d0000 {
671 reg = <0x020d0000 0x4000>;
672 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
673 };
674
675 epit2: epit@020d4000 {
676 reg = <0x020d4000 0x4000>;
677 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
678 };
679
680 src: src@020d8000 {
681 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
682 reg = <0x020d8000 0x4000>;
683 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
685 #reset-cells = <1>;
686 };
687
688 gpc: gpc@020dc000 {
689 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
690 reg = <0x020dc000 0x4000>;
691 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
692 };
693
694 iomuxc: iomuxc@020e0000 {
695 compatible = "fsl,imx6sx-iomuxc";
696 reg = <0x020e0000 0x4000>;
697 };
698
699 gpr: iomuxc-gpr@020e4000 {
700 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
701 reg = <0x020e4000 0x4000>;
702 };
703
704 sdma: sdma@020ec000 {
705 compatible = "fsl,imx6sx-sdma";
706 reg = <0x020ec000 0x4000>;
707 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clks IMX6SX_CLK_SDMA>,
709 <&clks IMX6SX_CLK_SDMA>;
710 clock-names = "ipg", "ahb";
711 #dma-cells = <3>;
712 };
713 };
714
715 aips2: aips-bus@02100000 {
716 compatible = "fsl,aips-bus", "simple-bus";
717 #address-cells = <1>;
718 #size-cells = <1>;
719 reg = <0x02100000 0x100000>;
720 ranges;
721
722 usbotg1: usb@02184000 {
723 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
724 reg = <0x02184000 0x200>;
725 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clks IMX6SX_CLK_USBOH3>;
727 fsl,usbphy = <&usbphy1>;
728 fsl,usbmisc = <&usbmisc 0>;
729 fsl,anatop = <&anatop>;
730 status = "disabled";
731 };
732
733 usbotg2: usb@02184200 {
734 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
735 reg = <0x02184200 0x200>;
736 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clks IMX6SX_CLK_USBOH3>;
738 fsl,usbphy = <&usbphy2>;
739 fsl,usbmisc = <&usbmisc 1>;
740 status = "disabled";
741 };
742
743 usbh: usb@02184400 {
744 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
745 reg = <0x02184400 0x200>;
746 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clks IMX6SX_CLK_USBOH3>;
748 fsl,usbmisc = <&usbmisc 2>;
749 phy_type = "hsic";
750 fsl,anatop = <&anatop>;
751 status = "disabled";
752 };
753
754 usbmisc: usbmisc@02184800 {
755 #index-cells = <1>;
756 compatible = "fsl,imx6sx-usbmisc";
757 reg = <0x02184800 0x200>;
758 clocks = <&clks IMX6SX_CLK_USBOH3>;
759 };
760
761 fec1: ethernet@02188000 {
762 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
763 reg = <0x02188000 0x4000>;
764 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clks IMX6SX_CLK_ENET>,
767 <&clks IMX6SX_CLK_ENET_AHB>,
768 <&clks IMX6SX_CLK_ENET_PTP>,
769 <&clks IMX6SX_CLK_ENET_REF>,
770 <&clks IMX6SX_CLK_ENET_PTP>;
771 clock-names = "ipg", "ahb", "ptp",
772 "enet_clk_ref", "enet_out";
773 status = "disabled";
774 };
775
776 mlb: mlb@0218c000 {
777 reg = <0x0218c000 0x4000>;
778 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clks IMX6SX_CLK_MLB>;
782 status = "disabled";
783 };
784
785 usdhc1: usdhc@02190000 {
786 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
787 reg = <0x02190000 0x4000>;
788 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&clks IMX6SX_CLK_USDHC1>,
790 <&clks IMX6SX_CLK_USDHC1>,
791 <&clks IMX6SX_CLK_USDHC1>;
792 clock-names = "ipg", "ahb", "per";
793 bus-width = <4>;
794 status = "disabled";
795 };
796
797 usdhc2: usdhc@02194000 {
798 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
799 reg = <0x02194000 0x4000>;
800 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clks IMX6SX_CLK_USDHC2>,
802 <&clks IMX6SX_CLK_USDHC2>,
803 <&clks IMX6SX_CLK_USDHC2>;
804 clock-names = "ipg", "ahb", "per";
805 bus-width = <4>;
806 status = "disabled";
807 };
808
809 usdhc3: usdhc@02198000 {
810 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
811 reg = <0x02198000 0x4000>;
812 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clks IMX6SX_CLK_USDHC3>,
814 <&clks IMX6SX_CLK_USDHC3>,
815 <&clks IMX6SX_CLK_USDHC3>;
816 clock-names = "ipg", "ahb", "per";
817 bus-width = <4>;
818 status = "disabled";
819 };
820
821 usdhc4: usdhc@0219c000 {
822 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
823 reg = <0x0219c000 0x4000>;
824 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6SX_CLK_USDHC4>,
826 <&clks IMX6SX_CLK_USDHC4>,
827 <&clks IMX6SX_CLK_USDHC4>;
828 clock-names = "ipg", "ahb", "per";
829 bus-width = <4>;
830 status = "disabled";
831 };
832
833 i2c1: i2c@021a0000 {
834 #address-cells = <1>;
835 #size-cells = <0>;
836 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
837 reg = <0x021a0000 0x4000>;
838 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX6SX_CLK_I2C1>;
840 status = "disabled";
841 };
842
843 i2c2: i2c@021a4000 {
844 #address-cells = <1>;
845 #size-cells = <0>;
846 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
847 reg = <0x021a4000 0x4000>;
848 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clks IMX6SX_CLK_I2C2>;
850 status = "disabled";
851 };
852
853 i2c3: i2c@021a8000 {
854 #address-cells = <1>;
855 #size-cells = <0>;
856 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
857 reg = <0x021a8000 0x4000>;
858 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clks IMX6SX_CLK_I2C3>;
860 status = "disabled";
861 };
862
863 mmdc: mmdc@021b0000 {
864 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
865 reg = <0x021b0000 0x4000>;
866 };
867
868 fec2: ethernet@021b4000 {
869 compatible = "fsl,imx6sx-fec";
870 reg = <0x021b4000 0x4000>;
871 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
872 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6SX_CLK_ENET>,
874 <&clks IMX6SX_CLK_ENET_AHB>,
875 <&clks IMX6SX_CLK_ENET_PTP>,
876 <&clks IMX6SX_CLK_ENET2_REF_125M>,
877 <&clks IMX6SX_CLK_ENET_PTP>;
878 clock-names = "ipg", "ahb", "ptp",
879 "enet_clk_ref", "enet_out";
880 status = "disabled";
881 };
882
883 weim: weim@021b8000 {
884 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
885 reg = <0x021b8000 0x4000>;
886 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
888 };
889
890 ocotp: ocotp@021bc000 {
891 compatible = "fsl,imx6sx-ocotp", "syscon";
892 reg = <0x021bc000 0x4000>;
893 clocks = <&clks IMX6SX_CLK_OCOTP>;
894 };
895
896 sai1: sai@021d4000 {
897 compatible = "fsl,imx6sx-sai";
898 reg = <0x021d4000 0x4000>;
899 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
901 <&clks IMX6SX_CLK_SAI1>,
902 <&clks 0>, <&clks 0>;
903 clock-names = "bus", "mclk1", "mclk2", "mclk3";
904 dma-names = "rx", "tx";
905 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
906 dma-source = <&gpr 0 15 0 16>;
907 status = "disabled";
908 };
909
910 audmux: audmux@021d8000 {
911 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
912 reg = <0x021d8000 0x4000>;
913 status = "disabled";
914 };
915
916 sai2: sai@021dc000 {
917 compatible = "fsl,imx6sx-sai";
918 reg = <0x021dc000 0x4000>;
919 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
921 <&clks IMX6SX_CLK_SAI2>,
922 <&clks 0>, <&clks 0>;
923 clock-names = "bus", "mclk1", "mclk2", "mclk3";
924 dma-names = "rx", "tx";
925 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
926 dma-source = <&gpr 0 17 0 18>;
927 status = "disabled";
928 };
929
930 qspi1: qspi@021e0000 {
931 #address-cells = <1>;
932 #size-cells = <0>;
933 compatible = "fsl,imx6sx-qspi";
934 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
935 reg-names = "QuadSPI", "QuadSPI-memory";
936 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clks IMX6SX_CLK_QSPI1>,
938 <&clks IMX6SX_CLK_QSPI1>;
939 clock-names = "qspi_en", "qspi";
940 status = "disabled";
941 };
942
943 qspi2: qspi@021e4000 {
944 #address-cells = <1>;
945 #size-cells = <0>;
946 compatible = "fsl,imx6sx-qspi";
947 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
948 reg-names = "QuadSPI", "QuadSPI-memory";
949 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clks IMX6SX_CLK_QSPI2>,
951 <&clks IMX6SX_CLK_QSPI2>;
952 clock-names = "qspi_en", "qspi";
953 status = "disabled";
954 };
955
956 uart2: serial@021e8000 {
957 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
958 reg = <0x021e8000 0x4000>;
959 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&clks IMX6SX_CLK_UART_IPG>,
961 <&clks IMX6SX_CLK_UART_SERIAL>;
962 clock-names = "ipg", "per";
963 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
964 dma-names = "rx", "tx";
965 status = "disabled";
966 };
967
968 uart3: serial@021ec000 {
969 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
970 reg = <0x021ec000 0x4000>;
971 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&clks IMX6SX_CLK_UART_IPG>,
973 <&clks IMX6SX_CLK_UART_SERIAL>;
974 clock-names = "ipg", "per";
975 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
976 dma-names = "rx", "tx";
977 status = "disabled";
978 };
979
980 uart4: serial@021f0000 {
981 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
982 reg = <0x021f0000 0x4000>;
983 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX6SX_CLK_UART_IPG>,
985 <&clks IMX6SX_CLK_UART_SERIAL>;
986 clock-names = "ipg", "per";
987 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
988 dma-names = "rx", "tx";
989 status = "disabled";
990 };
991
992 uart5: serial@021f4000 {
993 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
994 reg = <0x021f4000 0x4000>;
995 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6SX_CLK_UART_IPG>,
997 <&clks IMX6SX_CLK_UART_SERIAL>;
998 clock-names = "ipg", "per";
999 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1000 dma-names = "rx", "tx";
1001 status = "disabled";
1002 };
1003
1004 i2c4: i2c@021f8000 {
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1008 reg = <0x021f8000 0x4000>;
1009 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clks IMX6SX_CLK_I2C4>;
1011 status = "disabled";
1012 };
1013 };
1014
1015 aips3: aips-bus@02200000 {
1016 compatible = "fsl,aips-bus", "simple-bus";
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1019 reg = <0x02200000 0x100000>;
1020 ranges;
1021
1022 spba-bus@02200000 {
1023 compatible = "fsl,spba-bus", "simple-bus";
1024 #address-cells = <1>;
1025 #size-cells = <1>;
1026 reg = <0x02240000 0x40000>;
1027 ranges;
1028
1029 csi1: csi@02214000 {
1030 reg = <0x02214000 0x4000>;
1031 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1033 <&clks IMX6SX_CLK_CSI>,
1034 <&clks IMX6SX_CLK_DCIC1>;
1035 clock-names = "disp-axi", "csi_mclk", "dcic";
1036 status = "disabled";
1037 };
1038
1039 pxp: pxp@02218000 {
1040 reg = <0x02218000 0x4000>;
1041 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1043 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1044 clock-names = "pxp-axi", "disp-axi";
1045 status = "disabled";
1046 };
1047
1048 csi2: csi@0221c000 {
1049 reg = <0x0221c000 0x4000>;
1050 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1052 <&clks IMX6SX_CLK_CSI>,
1053 <&clks IMX6SX_CLK_DCIC2>;
1054 clock-names = "disp-axi", "csi_mclk", "dcic";
1055 status = "disabled";
1056 };
1057
1058 lcdif1: lcdif@02220000 {
1059 reg = <0x02220000 0x4000>;
1060 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1062 <&clks IMX6SX_CLK_LCDIF_APB>,
1063 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1064 clock-names = "pix", "axi", "disp_axi";
1065 status = "disabled";
1066 };
1067
1068 lcdif2: lcdif@02224000 {
1069 reg = <0x02224000 0x4000>;
1070 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1072 <&clks IMX6SX_CLK_LCDIF_APB>,
1073 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1074 clock-names = "pix", "axi", "disp_axi";
1075 status = "disabled";
1076 };
1077
1078 vadc: vadc@02228000 {
1079 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1080 reg-names = "vadc-vafe", "vadc-vdec";
1081 clocks = <&clks IMX6SX_CLK_VADC>,
1082 <&clks IMX6SX_CLK_CSI>;
1083 clock-names = "vadc", "csi";
1084 status = "disabled";
1085 };
1086 };
1087
1088 adc1: adc@02280000 {
1089 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1090 reg = <0x02280000 0x4000>;
1091 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&clks IMX6SX_CLK_IPG>;
1093 clock-names = "adc";
1094 status = "disabled";
1095 };
1096
1097 adc2: adc@02284000 {
1098 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1099 reg = <0x02284000 0x4000>;
1100 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1101 clocks = <&clks IMX6SX_CLK_IPG>;
1102 clock-names = "adc";
1103 status = "disabled";
1104 };
1105
1106 wdog3: wdog@02288000 {
1107 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1108 reg = <0x02288000 0x4000>;
1109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&clks IMX6SX_CLK_DUMMY>;
1111 status = "disabled";
1112 };
1113
1114 ecspi5: ecspi@0228c000 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1118 reg = <0x0228c000 0x4000>;
1119 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1121 <&clks IMX6SX_CLK_ECSPI5>;
1122 clock-names = "ipg", "per";
1123 status = "disabled";
1124 };
1125
1126 uart6: serial@022a0000 {
1127 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1128 reg = <0x022a0000 0x4000>;
1129 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1131 <&clks IMX6SX_CLK_UART_SERIAL>;
1132 clock-names = "ipg", "per";
1133 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1134 dma-names = "rx", "tx";
1135 status = "disabled";
1136 };
1137
1138 pwm5: pwm@022a4000 {
1139 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1140 reg = <0x022a4000 0x4000>;
1141 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&clks IMX6SX_CLK_PWM5>,
1143 <&clks IMX6SX_CLK_PWM5>;
1144 clock-names = "ipg", "per";
1145 #pwm-cells = <2>;
1146 };
1147
1148 pwm6: pwm@022a8000 {
1149 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1150 reg = <0x022a8000 0x4000>;
1151 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&clks IMX6SX_CLK_PWM6>,
1153 <&clks IMX6SX_CLK_PWM6>;
1154 clock-names = "ipg", "per";
1155 #pwm-cells = <2>;
1156 };
1157
1158 pwm7: pwm@022ac000 {
1159 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1160 reg = <0x022ac000 0x4000>;
1161 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clks IMX6SX_CLK_PWM7>,
1163 <&clks IMX6SX_CLK_PWM7>;
1164 clock-names = "ipg", "per";
1165 #pwm-cells = <2>;
1166 };
1167
1168 pwm8: pwm@0022b0000 {
1169 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1170 reg = <0x0022b0000 0x4000>;
1171 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&clks IMX6SX_CLK_PWM8>,
1173 <&clks IMX6SX_CLK_PWM8>;
1174 clock-names = "ipg", "per";
1175 #pwm-cells = <2>;
1176 };
1177 };
1178
1179 pcie: pcie@0x08000000 {
1180 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1181 reg = <0x08ffc000 0x4000>; /* DBI */
1182 #address-cells = <3>;
1183 #size-cells = <2>;
1184 device_type = "pci";
1185 /* configuration space */
1186 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1187 /* downstream I/O */
1188 0x81000000 0 0 0x08f80000 0 0x00010000
1189 /* non-prefetchable memory */
1190 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1191 num-lanes = <1>;
1192 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1194 <&clks IMX6SX_CLK_PCIE_AXI>,
1195 <&clks IMX6SX_CLK_LVDS1_OUT>,
1196 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1197 clock-names = "pcie_ref_125m", "pcie_axi",
1198 "lvds_gate", "display_axi";
1199 status = "disabled";
1200 };
1201 };
1202};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 15:58:22 -0500