diff options
| author | Anson Huang <b20788@freescale.com> | 2013-12-16 16:07:37 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-02-09 08:29:35 -0500 |
| commit | 26ea58019edabe4f36d4d531518231d6856d8a00 (patch) | |
| tree | b874ea4abd62faa3ff66e79644bd4896bb415b9d /arch/arm/boot/dts/imx6q.dtsi | |
| parent | da474d4c07f2eb665b80844e5f2ff415969bbb79 (diff) | |
ARM: dts: imx6q: update setting of VDDARM_CAP voltage
According to datasheet, VDD_CACHE_CAP must not exceed VDDARM_CAP
by more than 200mV, as all of i.MX6Q boards' VDD_CACHE_CAP currently
are connected to VDDSOC_CAP, so we need to follow this rule by
increasing VDDARM_CAP's voltage.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9581ae4a6c20..7acfda7f5868 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -27,7 +27,7 @@ | |||
| 27 | 1200000 1275000 | 27 | 1200000 1275000 |
| 28 | 996000 1250000 | 28 | 996000 1250000 |
| 29 | 792000 1150000 | 29 | 792000 1150000 |
| 30 | 396000 950000 | 30 | 396000 975000 |
| 31 | >; | 31 | >; |
| 32 | clock-latency = <61036>; /* two CLK32 periods */ | 32 | clock-latency = <61036>; /* two CLK32 periods */ |
| 33 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, | 33 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, |