ARM: dts: Phytec imx6q pfla02 and pbab01 support

Add support for imx6q Phytec phyFLEX-i.MX6 Quad (aka pfla02 and pbab01).
 - Module pfla02
 - Carrier-Board pbab01

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 74 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..f5e1981025ed
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+        model = "Phytec phyFLEX-i.MX6 Ouad";
+        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+                        >;
+                };
+        };
+
+        pfla02 {
+                pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+                        fsl,pins = <
+                                MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
+                                MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+                        >;
+                };
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_3>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 0>;
+        status = "disabled";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "disabled";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        cd-gpios = <&gpio1 4 0>;
+        wp-gpios = <&gpio1 2 0>;
+        status = "disabled";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2
+                     &pinctrl_usdhc3_pfla02>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};