diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2013-02-19 21:32:52 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-04-09 10:52:50 -0400 |
| commit | e16415313c9b00b1adc313e85c2c8a81febe0b98 (patch) | |
| tree | b1e804b1bb647f3984036d9f9befbe53023bc519 /arch/arm/boot/dts/imx53-mba53.dts | |
| parent | 36dffd8f49bc1364998db81bee739ea4574d88f7 (diff) | |
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx53-mba53.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx53-mba53.dts | 80 |
1 files changed, 43 insertions, 37 deletions
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 4e04710ac7b9..445a01119cc5 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts | |||
| @@ -21,51 +21,57 @@ | |||
| 21 | &iomuxc { | 21 | &iomuxc { |
| 22 | lvds1 { | 22 | lvds1 { |
| 23 | pinctrl_lvds1_1: lvds1-grp1 { | 23 | pinctrl_lvds1_1: lvds1-grp1 { |
| 24 | fsl,pins = <730 0x10000 /* LVDS0_TX3 */ | 24 | fsl,pins = < |
| 25 | 732 0x10000 /* LVDS0_CLK */ | 25 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000 |
| 26 | 734 0x10000 /* LVDS0_TX2 */ | 26 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000 |
| 27 | 736 0x10000 /* LVDS0_TX1 */ | 27 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000 |
| 28 | 738 0x10000>; /* LVDS0_TX0 */ | 28 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000 |
| 29 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000 | ||
| 30 | >; | ||
| 29 | }; | 31 | }; |
| 30 | 32 | ||
| 31 | pinctrl_lvds1_2: lvds1-grp2 { | 33 | pinctrl_lvds1_2: lvds1-grp2 { |
| 32 | fsl,pins = <720 0x10000 /* LVDS1_TX3 */ | 34 | fsl,pins = < |
| 33 | 722 0x10000 /* LVDS1_TX2 */ | 35 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000 |
| 34 | 724 0x10000 /* LVDS1_CLK */ | 36 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000 |
| 35 | 726 0x10000 /* LVDS1_TX1 */ | 37 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000 |
| 36 | 728 0x10000>; /* LVDS1_TX0 */ | 38 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000 |
| 39 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000 | ||
| 40 | >; | ||
| 37 | }; | 41 | }; |
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| 40 | disp1 { | 44 | disp1 { |
| 41 | pinctrl_disp1_1: disp1-grp1 { | 45 | pinctrl_disp1_1: disp1-grp1 { |
| 42 | fsl,pins = <689 0x10000 /* DISP1_DRDY */ | 46 | fsl,pins = < |
| 43 | 482 0x10000 /* DISP1_HSYNC */ | 47 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */ |
| 44 | 489 0x10000 /* DISP1_VSYNC */ | 48 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */ |
| 45 | 515 0x10000 /* DISP1_DAT_22 */ | 49 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */ |
| 46 | 523 0x10000 /* DISP1_DAT_23 */ | 50 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000 |
| 47 | 545 0x10000 /* DISP1_DAT_21 */ | 51 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000 |
| 48 | 553 0x10000 /* DISP1_DAT_20 */ | 52 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000 |
| 49 | 558 0x10000 /* DISP1_DAT_19 */ | 53 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000 |
| 50 | 564 0x10000 /* DISP1_DAT_18 */ | 54 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000 |
| 51 | 570 0x10000 /* DISP1_DAT_17 */ | 55 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000 |
| 52 | 575 0x10000 /* DISP1_DAT_16 */ | 56 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000 |
| 53 | 580 0x10000 /* DISP1_DAT_15 */ | 57 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000 |
| 54 | 585 0x10000 /* DISP1_DAT_14 */ | 58 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000 |
| 55 | 590 0x10000 /* DISP1_DAT_13 */ | 59 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000 |
| 56 | 595 0x10000 /* DISP1_DAT_12 */ | 60 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000 |
| 57 | 628 0x10000 /* DISP1_DAT_11 */ | 61 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000 |
| 58 | 634 0x10000 /* DISP1_DAT_10 */ | 62 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000 |
| 59 | 639 0x10000 /* DISP1_DAT_9 */ | 63 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000 |
| 60 | 644 0x10000 /* DISP1_DAT_8 */ | 64 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000 |
| 61 | 649 0x10000 /* DISP1_DAT_7 */ | 65 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000 |
| 62 | 654 0x10000 /* DISP1_DAT_6 */ | 66 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000 |
| 63 | 659 0x10000 /* DISP1_DAT_5 */ | 67 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000 |
| 64 | 664 0x10000 /* DISP1_DAT_4 */ | 68 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000 |
| 65 | 669 0x10000 /* DISP1_DAT_3 */ | 69 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000 |
| 66 | 674 0x10000 /* DISP1_DAT_2 */ | 70 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000 |
| 67 | 679 0x10000 /* DISP1_DAT_1 */ | 71 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000 |
| 68 | 684 0x10000>; /* DISP1_DAT_0 */ | 72 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000 |
| 73 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000 | ||
| 74 | >; | ||
| 69 | }; | 75 | }; |
| 70 | }; | 76 | }; |
| 71 | }; | 77 | }; |