diff options
| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-06-04 07:07:14 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-06-17 04:04:28 -0400 |
| commit | 188e97db02c581918ea0130f6a6fd903feb9b4a5 (patch) | |
| tree | cad30165e99b04b3a9a2616cb6c54eeb992fa0db /arch/arm/boot/dts/imx53-mba53.dts | |
| parent | deb19eb77dd44e2f7caf900b89499d7488c6ce66 (diff) | |
ARM i.MX53: mba53: fix lvds/disp pinctrl
use NO_PAD_CTL / 0x80000000 instead of 0x10000 to prevent misconfigured pads
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
[Steffen: split up patch into tqma53+mba53 part]
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx53-mba53.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx53-mba53.dts | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 4515d0124990..869aa3eb3c7d 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts | |||
| @@ -76,21 +76,21 @@ | |||
| 76 | lvds1 { | 76 | lvds1 { |
| 77 | pinctrl_lvds1_1: lvds1-grp1 { | 77 | pinctrl_lvds1_1: lvds1-grp1 { |
| 78 | fsl,pins = < | 78 | fsl,pins = < |
| 79 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000 | 79 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 |
| 80 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000 | 80 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 |
| 81 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000 | 81 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 |
| 82 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000 | 82 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 |
| 83 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000 | 83 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 |
| 84 | >; | 84 | >; |
| 85 | }; | 85 | }; |
| 86 | 86 | ||
| 87 | pinctrl_lvds1_2: lvds1-grp2 { | 87 | pinctrl_lvds1_2: lvds1-grp2 { |
| 88 | fsl,pins = < | 88 | fsl,pins = < |
| 89 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000 | 89 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 |
| 90 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000 | 90 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 |
| 91 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000 | 91 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 |
| 92 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000 | 92 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 |
| 93 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000 | 93 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 |
| 94 | >; | 94 | >; |
| 95 | }; | 95 | }; |
| 96 | }; | 96 | }; |
| @@ -98,33 +98,33 @@ | |||
| 98 | disp1 { | 98 | disp1 { |
| 99 | pinctrl_disp1_1: disp1-grp1 { | 99 | pinctrl_disp1_1: disp1-grp1 { |
| 100 | fsl,pins = < | 100 | fsl,pins = < |
| 101 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */ | 101 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ |
| 102 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */ | 102 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ |
| 103 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */ | 103 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ |
| 104 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000 | 104 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 |
| 105 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000 | 105 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 |
| 106 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000 | 106 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 |
| 107 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000 | 107 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 |
| 108 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000 | 108 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 |
| 109 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000 | 109 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 |
| 110 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000 | 110 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 |
| 111 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000 | 111 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 |
| 112 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000 | 112 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 |
| 113 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000 | 113 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 |
| 114 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000 | 114 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 |
| 115 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000 | 115 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 |
| 116 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000 | 116 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 |
| 117 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000 | 117 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 |
| 118 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000 | 118 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 |
| 119 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000 | 119 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 |
| 120 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000 | 120 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 |
| 121 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000 | 121 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 |
| 122 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000 | 122 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 |
| 123 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000 | 123 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 |
| 124 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000 | 124 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 |
| 125 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000 | 125 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 |
| 126 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000 | 126 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 |
| 127 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000 | 127 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 |
| 128 | >; | 128 | >; |
| 129 | }; | 129 | }; |
| 130 | }; | 130 | }; |