diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-05-10 11:47:35 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@freescale.com> | 2014-05-16 11:02:12 -0400 |
commit | 75416cfebc9ae5d35689fcc0a72d384a26871f8e (patch) | |
tree | 93e8ebd9b4ada24c7a865fa951cf650c3868a39d /arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | |
parent | ec55b150879fe97f9fd62befcac95119f5467e79 (diff) |
ARM: dts: imx51-eukrea-mbimxsd51-baseboard: Add CAN support
Add support for CAN based on a MCP2515 connected to ECSPI1.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Eric BĂ©nard <eric@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts')
-rw-r--r-- | arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 8b1098ebaf79..75e66c9c6144 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | |||
@@ -24,6 +24,14 @@ | |||
24 | model = "Eukrea CPUIMX51"; | 24 | model = "Eukrea CPUIMX51"; |
25 | compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; | 25 | compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; |
26 | 26 | ||
27 | clocks { | ||
28 | clk24M: can_clock { | ||
29 | compatible = "fixed-clock"; | ||
30 | #clock-cells = <0>; | ||
31 | clock-frequency = <24000000>; | ||
32 | }; | ||
33 | }; | ||
34 | |||
27 | gpio_keys { | 35 | gpio_keys { |
28 | compatible = "gpio-keys"; | 36 | compatible = "gpio-keys"; |
29 | pinctrl-names = "default"; | 37 | pinctrl-names = "default"; |
@@ -50,6 +58,23 @@ | |||
50 | }; | 58 | }; |
51 | }; | 59 | }; |
52 | 60 | ||
61 | regulators { | ||
62 | compatible = "simple-bus"; | ||
63 | #address-cells = <1>; | ||
64 | #size-cells = <0>; | ||
65 | |||
66 | reg_can: regulator@0 { | ||
67 | compatible = "regulator-fixed"; | ||
68 | reg = <0>; | ||
69 | regulator-name = "CAN_RST"; | ||
70 | regulator-min-microvolt = <3300000>; | ||
71 | regulator-max-microvolt = <3300000>; | ||
72 | gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; | ||
73 | startup-delay-us = <20000>; | ||
74 | enable-active-high; | ||
75 | }; | ||
76 | }; | ||
77 | |||
53 | sound { | 78 | sound { |
54 | compatible = "eukrea,asoc-tlv320"; | 79 | compatible = "eukrea,asoc-tlv320"; |
55 | eukrea,model = "imx51-eukrea-tlv320aic23"; | 80 | eukrea,model = "imx51-eukrea-tlv320aic23"; |
@@ -86,6 +111,26 @@ | |||
86 | status = "okay"; | 111 | status = "okay"; |
87 | }; | 112 | }; |
88 | 113 | ||
114 | &ecspi1 { | ||
115 | pinctrl-names = "default"; | ||
116 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
117 | fsl,spi-num-chipselects = <1>; | ||
118 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; | ||
119 | status = "okay"; | ||
120 | |||
121 | can0: can@0 { | ||
122 | pinctrl-names = "default"; | ||
123 | pinctrl-0 = <&pinctrl_can>; | ||
124 | compatible = "microchip,mcp2515"; | ||
125 | reg = <0>; | ||
126 | clocks = <&clk24M>; | ||
127 | spi-max-frequency = <10000000>; | ||
128 | interrupt-parent = <&gpio1>; | ||
129 | interrupts = <1 IRQ_TYPE_EDGE_FALLING>; | ||
130 | vdd-supply = <®_can>; | ||
131 | }; | ||
132 | }; | ||
133 | |||
89 | &i2c1 { | 134 | &i2c1 { |
90 | tlv320aic23: codec@1a { | 135 | tlv320aic23: codec@1a { |
91 | compatible = "ti,tlv320aic23"; | 136 | compatible = "ti,tlv320aic23"; |
@@ -104,6 +149,23 @@ | |||
104 | >; | 149 | >; |
105 | }; | 150 | }; |
106 | 151 | ||
152 | |||
153 | pinctrl_can: cangrp { | ||
154 | fsl,pins = < | ||
155 | MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ | ||
156 | MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ | ||
157 | >; | ||
158 | }; | ||
159 | |||
160 | pinctrl_ecspi1: ecspi1grp { | ||
161 | fsl,pins = < | ||
162 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
163 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
164 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
165 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ | ||
166 | >; | ||
167 | }; | ||
168 | |||
107 | pinctrl_esdhc1: esdhc1grp { | 169 | pinctrl_esdhc1: esdhc1grp { |
108 | fsl,pins = < | 170 | fsl,pins = < |
109 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | 171 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |