ARM: dts: imx27 phycore pinctrl

Add pinctrl nodes and properties for phycore device nodes.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 39 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index 648541a33e8d..87719288d0ea 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -135,11 +135,15 @@
 
 &fec {
         phy-reset-gpios = <&gpio3 30 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
         status = "okay";
 };
 
 &i2c2 {
         clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
         status = "okay";
 
         at24@52 {
@@ -159,6 +163,41 @@
         };
 };
 
+&iomuxc {
+        imx27_phycore_som {
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                                MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                                MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                                MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                                MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                                MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                                MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                                MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                                MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                                MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                                MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                                MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                                MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                                MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                                MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                                MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                                MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                                MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                                MX27_PAD_SSI3_TXDAT__GPIO3_30   0x0 /* FEC RST */
+                        >;
+                };
+
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                                MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                        >;
+                };
+        };
+};
+
 &nfc {
         nand-bus-width = <8>;
         nand-ecc-mode = "hw";