ARM: dts: fix L2 address in Hi3620

Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index ab1116d086be..83a5b8685bd9 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -73,7 +73,7 @@
 
                 L2: l2-cache {
                         compatible = "arm,pl310-cache";
-                        reg = <0xfc10000 0x100000>;
+                        reg = <0x100000 0x100000>;
                         interrupts = <0 15 4>;
                         cache-unified;
                         cache-level = <2>;