ARM: dts: add dts file for exynos5800-peach-pi board

Adds support for google peach-pi board having the
Exynos5800 SoC.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 144 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
new file mode 100644
index 000000000000..4ed9ccc24e52
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -0,0 +1,144 @@
+/*
+ * Google Peach Pi Rev 10+ board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "exynos5800.dtsi"
+
+/ {
+        model = "Google Peach Pi Rev 10+";
+
+        compatible = "google,pi-rev16",
+                "google,pi-rev15", "google,pi-rev14",
+                "google,pi-rev13", "google,pi-rev12",
+                "google,pi-rev11", "google,pi-rev10",
+                "google,pi", "google,peach", "samsung,exynos5800",
+                "samsung,exynos5";
+
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&power_key_irq>;
+
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 1000000 0>;
+                brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+                default-brightness-level = <7>;
+                pinctrl-0 = <&pwm0_out>;
+                pinctrl-names = "default";
+        };
+};
+
+&pinctrl_0 {
+        tpm_irq: tpm-irq {
+                samsung,pins = "gpx1-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        power_key_irq: power-key-irq {
+                samsung,pins = "gpx1-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+&uart_3 {
+        status = "okay";
+};
+
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        caps2-mmc-hs200-1_8v;
+        supports-highspeed;
+        non-removable;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+        };
+};
+
+&hsi2c_9 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tpm@20 {
+                compatible = "infineon,slb9645tt";
+                reg = <0x20>;
+                /* Unused irq; but still need to configure the pins */
+                pinctrl-names = "default";
+                pinctrl-0 = <&tpm_irq>;
+        };
+};
+
+/*
+ * Use longest HW watchdog in SoC (32 seconds) since the hardware
+ * watchdog provides no debugging information (compared to soft/hard
+ * lockup detectors) and so should be last resort.
+ */
+&watchdog {
+        timeout-sec = <32>;
+};