diff options
author | Javier Martinez Canillas <javier.martinez@collabora.co.uk> | 2014-09-13 11:47:22 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2014-09-13 11:47:22 -0400 |
commit | 8be6a6d04ceae15de160ca4cbc0915baaee801e4 (patch) | |
tree | ea6b6ea245b378d977f59f7677bf0ce168522be8 /arch/arm/boot/dts/exynos5420-peach-pit.dts | |
parent | dc0cf1a3ecd53c55aecd7182bce15843ca29c895 (diff) |
ARM: dts: Set i2c7 clock at 400kHz for exynos based Peach boards
The downstream ChromeOS 3.8 kernel sets the clock frequency
for the I2C bus 7 at 400kHz. Do the same change in mainline.
Suggested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420-peach-pit.dts')
-rw-r--r-- | arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index b8fea56b16a0..f24770937ec0 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts | |||
@@ -489,6 +489,7 @@ | |||
489 | 489 | ||
490 | &hsi2c_7 { | 490 | &hsi2c_7 { |
491 | status = "okay"; | 491 | status = "okay"; |
492 | clock-frequency = <400000>; | ||
492 | 493 | ||
493 | max98090: codec@10 { | 494 | max98090: codec@10 { |
494 | compatible = "maxim,max98090"; | 495 | compatible = "maxim,max98090"; |