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authorYuvaraj Kumar C D <yuvaraj.cd@samsung.com>2014-03-17 18:49:14 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-03-17 18:49:14 -0400
commitba0d7ed391b7b3fb5ca98d9cf4d067b7f5ed956b (patch)
treec4ef7983ba455208a9952b39046f9344708efd25 /arch/arm/boot/dts/exynos5250.dtsi
parent183af2522da5d02fd1d682e105ee4d60a685c05e (diff)
ARM: dts: enable ahci sata and sata phy for exynos5250
This patch adds dt entry for ahci sata controller and its corresponding phy controller.phy node has been added w.r.t new generic phy framework. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5250.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi18
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9ecffcb1fe91..fdeed7c29ac9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -47,6 +47,7 @@
47 i2c6 = &i2c_6; 47 i2c6 = &i2c_6;
48 i2c7 = &i2c_7; 48 i2c7 = &i2c_7;
49 i2c8 = &i2c_8; 49 i2c8 = &i2c_8;
50 i2c9 = &i2c_9;
50 pinctrl0 = &pinctrl_0; 51 pinctrl0 = &pinctrl_0;
51 pinctrl1 = &pinctrl_1; 52 pinctrl1 = &pinctrl_1;
52 pinctrl2 = &pinctrl_2; 53 pinctrl2 = &pinctrl_2;
@@ -235,16 +236,25 @@
235 }; 236 };
236 237
237 sata@122F0000 { 238 sata@122F0000 {
238 compatible = "samsung,exynos5-sata-ahci"; 239 compatible = "snps,dwc-ahci";
240 samsung,sata-freq = <66>;
239 reg = <0x122F0000 0x1ff>; 241 reg = <0x122F0000 0x1ff>;
240 interrupts = <0 115 0>; 242 interrupts = <0 115 0>;
241 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 243 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
242 clock-names = "sata", "sclk_sata"; 244 clock-names = "sata", "sclk_sata";
245 phys = <&sata_phy>;
246 phy-names = "sata-phy";
247 status = "disabled";
243 }; 248 };
244 249
245 sata-phy@12170000 { 250 sata_phy: sata-phy@12170000 {
246 compatible = "samsung,exynos5-sata-phy"; 251 compatible = "samsung,exynos5250-sata-phy";
247 reg = <0x12170000 0x1ff>; 252 reg = <0x12170000 0x1ff>;
253 clocks = <&clock 287>;
254 clock-names = "sata_phyctrl";
255 #phy-cells = <0>;
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 status = "disabled";
248 }; 258 };
249 259
250 i2c_0: i2c@12C60000 { 260 i2c_0: i2c@12C60000 {
@@ -362,7 +372,7 @@
362 status = "disabled"; 372 status = "disabled";
363 }; 373 };
364 374
365 i2c@121D0000 { 375 i2c_9: i2c@121D0000 {
366 compatible = "samsung,exynos5-sata-phy-i2c"; 376 compatible = "samsung,exynos5-sata-phy-i2c";
367 reg = <0x121D0000 0x100>; 377 reg = <0x121D0000 0x100>;
368 #address-cells = <1>; 378 #address-cells = <1>;