From ba0d7ed391b7b3fb5ca98d9cf4d067b7f5ed956b Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Date: Tue, 18 Mar 2014 07:49:14 +0900 Subject: ARM: dts: enable ahci sata and sata phy for exynos5250 This patch adds dt entry for ahci sata controller and its corresponding phy controller.phy node has been added w.r.t new generic phy framework. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> --- arch/arm/boot/dts/exynos5250.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts/exynos5250.dtsi') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9ecffcb1fe91..fdeed7c29ac9 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -47,6 +47,7 @@ i2c6 = &i2c_6; i2c7 = &i2c_7; i2c8 = &i2c_8; + i2c9 = &i2c_9; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -235,16 +236,25 @@ }; sata@122F0000 { - compatible = "samsung,exynos5-sata-ahci"; + compatible = "snps,dwc-ahci"; + samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; interrupts = <0 115 0>; clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; clock-names = "sata", "sclk_sata"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; }; - sata-phy@12170000 { - compatible = "samsung,exynos5-sata-phy"; + sata_phy: sata-phy@12170000 { + compatible = "samsung,exynos5250-sata-phy"; reg = <0x12170000 0x1ff>; + clocks = <&clock 287>; + clock-names = "sata_phyctrl"; + #phy-cells = <0>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; }; i2c_0: i2c@12C60000 { @@ -362,7 +372,7 @@ status = "disabled"; }; - i2c@121D0000 { + i2c_9: i2c@121D0000 { compatible = "samsung,exynos5-sata-phy-i2c"; reg = <0x121D0000 0x100>; #address-cells = <1>; -- cgit v1.2.2