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authorChanwoo Choi <cw00.choi@samsung.com>2014-03-17 17:25:59 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-03-17 17:25:59 -0400
commit8bdfa203c5827da811ed01dd19ba452135d21bee (patch)
treea8bc6857f8e8c9f8a4cfa0c9e365095b2c7f4c2d /arch/arm/boot/dts/exynos4212.dtsi
parent10ea1f18334ebf353ec283bba6f78c882281fcb2 (diff)
ARM: dts: Move common dt data for interrupt combiner controller for exynos4x12
This patch move common dt data of interrupt combiner controller to exynos4x12.dtsi. Each Exynos4x12 SoC has different number of interrput combiner as following: - Exynos4212 : interrput combiner 18(0 ~ 17) - Exynos4412 : interrput combiner 20(0 ~ 19) The exynos combiner driver initialize interrupt according to specific number of interrput combiner. - samsung,combiner-nr : The number of interrput combiners supported. Also, This patch arrange again the dt data according to register address in exynos4212/exynos4412.dtsi. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos4212.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi13
1 files changed, 4 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 94a43f9a05e2..ceefc711793c 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,16 +22,11 @@
22/ { 22/ {
23 compatible = "samsung,exynos4212"; 23 compatible = "samsung,exynos4212";
24 24
25 gic: interrupt-controller@10490000 { 25 combiner: interrupt-controller@10440000 {
26 cpu-offset = <0x8000>; 26 samsung,combiner-nr = <18>;
27 }; 27 };
28 28
29 interrupt-controller@10440000 { 29 gic: interrupt-controller@10490000 {
30 samsung,combiner-nr = <18>; 30 cpu-offset = <0x8000>;
31 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
32 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
33 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
34 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
35 <0 107 0>, <0 108 0>;
36 }; 31 };
37}; 32};