diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-04-22 12:24:55 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-04-22 12:24:55 -0400 |
commit | 8b3c8ba3d8c2680dab5363a80c024965cac08b1e (patch) | |
tree | 18150efb36891e6e76e2cad89c1b2fcc5faeae93 /arch/arm/boot/dts/dra7.dtsi | |
parent | d34dc4f9e88e4b6beefb819e4e743fd6160a9b75 (diff) | |
parent | 48c1078509b47b38802329028ccfd77783bcff99 (diff) |
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Olof Johansson:
"We were expecting to sit on this branch through most of the merge
window since the contents was merged into our tree late, but we ended
up sitting on all of our contents so it can go in with the rest.
The contents here is:
- a large branch of cleanups of the CM/PRM blocks on OMAP.
- a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- a branch with DT updates for Freescale i.MX. including some
shuffling from .dts to .dtsi (include) files that causes a little
churn"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
ARM: OMAP4+: control: add support for initializing control module via DT
ARM: dts: dra7: add minimal l4 bus layout with control module support
ARM: dts: omap5: add minimal l4 bus layout with control module support
ARM: OMAP4+: control: remove support for legacy pad read/write
ARM: OMAP4: display: convert display to use syscon for dsi muxing
ARM: dts: omap4: add minimal l4 bus layout with control module support
ARM: dts: am4372: add minimal l4 bus layout with control module support
ARM: dts: am43xx-epos-evm: fix pinmux node layout
ARM: dts: am33xx: add minimal l4 bus layout with control module support
ARM: dts: omap3: add minimal l4 bus layout with control module support
ARM: dts: omap24xx: add minimal l4 bus layout with control module support
ARM: OMAP2+: control: add syscon support for register accesses
ARM: OMAP2+: id: cache omap_type value
ARM: OMAP2+: control: remove API for getting control module base address
ARM: OMAP2+: clock: add low-level support for regmap
ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
ARM: OMAP2+: CM: move SoC specific init calls within a generic API
ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
...
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
-rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 156 |
1 files changed, 93 insertions, 63 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 082882c616e8..5332b57b4950 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
@@ -102,17 +102,101 @@ | |||
102 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | 102 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
103 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | 103 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
104 | 104 | ||
105 | prm: prm@4ae06000 { | 105 | l4_cfg: l4@4a000000 { |
106 | compatible = "ti,dra7-prm"; | 106 | compatible = "ti,dra7-l4-cfg", "simple-bus"; |
107 | reg = <0x4ae06000 0x3000>; | 107 | #address-cells = <1>; |
108 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | 108 | #size-cells = <1>; |
109 | ranges = <0 0x4a000000 0x22c000>; | ||
109 | 110 | ||
110 | prm_clocks: clocks { | 111 | scm: scm@2000 { |
112 | compatible = "ti,dra7-scm-core", "simple-bus"; | ||
113 | reg = <0x2000 0x2000>; | ||
111 | #address-cells = <1>; | 114 | #address-cells = <1>; |
112 | #size-cells = <0>; | 115 | #size-cells = <1>; |
116 | ranges = <0 0x2000 0x2000>; | ||
117 | |||
118 | scm_conf: scm_conf@0 { | ||
119 | compatible = "syscon"; | ||
120 | reg = <0x0 0x1400>; | ||
121 | #address-cells = <1>; | ||
122 | #size-cells = <1>; | ||
123 | |||
124 | pbias_regulator: pbias_regulator { | ||
125 | compatible = "ti,pbias-omap"; | ||
126 | reg = <0xe00 0x4>; | ||
127 | syscon = <&scm_conf>; | ||
128 | pbias_mmc_reg: pbias_mmc_omap5 { | ||
129 | regulator-name = "pbias_mmc_omap5"; | ||
130 | regulator-min-microvolt = <1800000>; | ||
131 | regulator-max-microvolt = <3000000>; | ||
132 | }; | ||
133 | }; | ||
134 | }; | ||
135 | |||
136 | dra7_pmx_core: pinmux@1400 { | ||
137 | compatible = "ti,dra7-padconf", | ||
138 | "pinctrl-single"; | ||
139 | reg = <0x1400 0x0464>; | ||
140 | #address-cells = <1>; | ||
141 | #size-cells = <0>; | ||
142 | #interrupt-cells = <1>; | ||
143 | interrupt-controller; | ||
144 | pinctrl-single,register-width = <32>; | ||
145 | pinctrl-single,function-mask = <0x3fffffff>; | ||
146 | }; | ||
147 | }; | ||
148 | |||
149 | cm_core_aon: cm_core_aon@5000 { | ||
150 | compatible = "ti,dra7-cm-core-aon"; | ||
151 | reg = <0x5000 0x2000>; | ||
152 | |||
153 | cm_core_aon_clocks: clocks { | ||
154 | #address-cells = <1>; | ||
155 | #size-cells = <0>; | ||
156 | }; | ||
157 | |||
158 | cm_core_aon_clockdomains: clockdomains { | ||
159 | }; | ||
113 | }; | 160 | }; |
114 | 161 | ||
115 | prm_clockdomains: clockdomains { | 162 | cm_core: cm_core@8000 { |
163 | compatible = "ti,dra7-cm-core"; | ||
164 | reg = <0x8000 0x3000>; | ||
165 | |||
166 | cm_core_clocks: clocks { | ||
167 | #address-cells = <1>; | ||
168 | #size-cells = <0>; | ||
169 | }; | ||
170 | |||
171 | cm_core_clockdomains: clockdomains { | ||
172 | }; | ||
173 | }; | ||
174 | }; | ||
175 | |||
176 | l4_wkup: l4@4ae00000 { | ||
177 | compatible = "ti,dra7-l4-wkup", "simple-bus"; | ||
178 | #address-cells = <1>; | ||
179 | #size-cells = <1>; | ||
180 | ranges = <0 0x4ae00000 0x3f000>; | ||
181 | |||
182 | counter32k: counter@4000 { | ||
183 | compatible = "ti,omap-counter32k"; | ||
184 | reg = <0x4000 0x40>; | ||
185 | ti,hwmods = "counter_32k"; | ||
186 | }; | ||
187 | |||
188 | prm: prm@6000 { | ||
189 | compatible = "ti,dra7-prm"; | ||
190 | reg = <0x6000 0x3000>; | ||
191 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | ||
192 | |||
193 | prm_clocks: clocks { | ||
194 | #address-cells = <1>; | ||
195 | #size-cells = <0>; | ||
196 | }; | ||
197 | |||
198 | prm_clockdomains: clockdomains { | ||
199 | }; | ||
116 | }; | 200 | }; |
117 | }; | 201 | }; |
118 | 202 | ||
@@ -197,38 +281,6 @@ | |||
197 | #thermal-sensor-cells = <1>; | 281 | #thermal-sensor-cells = <1>; |
198 | }; | 282 | }; |
199 | 283 | ||
200 | cm_core_aon: cm_core_aon@4a005000 { | ||
201 | compatible = "ti,dra7-cm-core-aon"; | ||
202 | reg = <0x4a005000 0x2000>; | ||
203 | |||
204 | cm_core_aon_clocks: clocks { | ||
205 | #address-cells = <1>; | ||
206 | #size-cells = <0>; | ||
207 | }; | ||
208 | |||
209 | cm_core_aon_clockdomains: clockdomains { | ||
210 | }; | ||
211 | }; | ||
212 | |||
213 | cm_core: cm_core@4a008000 { | ||
214 | compatible = "ti,dra7-cm-core"; | ||
215 | reg = <0x4a008000 0x3000>; | ||
216 | |||
217 | cm_core_clocks: clocks { | ||
218 | #address-cells = <1>; | ||
219 | #size-cells = <0>; | ||
220 | }; | ||
221 | |||
222 | cm_core_clockdomains: clockdomains { | ||
223 | }; | ||
224 | }; | ||
225 | |||
226 | counter32k: counter@4ae04000 { | ||
227 | compatible = "ti,omap-counter32k"; | ||
228 | reg = <0x4ae04000 0x40>; | ||
229 | ti,hwmods = "counter_32k"; | ||
230 | }; | ||
231 | |||
232 | dra7_ctrl_core: ctrl_core@4a002000 { | 284 | dra7_ctrl_core: ctrl_core@4a002000 { |
233 | compatible = "syscon"; | 285 | compatible = "syscon"; |
234 | reg = <0x4a002000 0x6d0>; | 286 | reg = <0x4a002000 0x6d0>; |
@@ -239,28 +291,6 @@ | |||
239 | reg = <0x4a002e00 0x7c>; | 291 | reg = <0x4a002e00 0x7c>; |
240 | }; | 292 | }; |
241 | 293 | ||
242 | pbias_regulator: pbias_regulator { | ||
243 | compatible = "ti,pbias-omap"; | ||
244 | reg = <0 0x4>; | ||
245 | syscon = <&dra7_ctrl_general>; | ||
246 | pbias_mmc_reg: pbias_mmc_omap5 { | ||
247 | regulator-name = "pbias_mmc_omap5"; | ||
248 | regulator-min-microvolt = <1800000>; | ||
249 | regulator-max-microvolt = <3000000>; | ||
250 | }; | ||
251 | }; | ||
252 | |||
253 | dra7_pmx_core: pinmux@4a003400 { | ||
254 | compatible = "ti,dra7-padconf", "pinctrl-single"; | ||
255 | reg = <0x4a003400 0x0464>; | ||
256 | #address-cells = <1>; | ||
257 | #size-cells = <0>; | ||
258 | #interrupt-cells = <1>; | ||
259 | interrupt-controller; | ||
260 | pinctrl-single,register-width = <32>; | ||
261 | pinctrl-single,function-mask = <0x3fffffff>; | ||
262 | }; | ||
263 | |||
264 | sdma: dma-controller@4a056000 { | 294 | sdma: dma-controller@4a056000 { |
265 | compatible = "ti,omap4430-sdma"; | 295 | compatible = "ti,omap4430-sdma"; |
266 | reg = <0x4a056000 0x1000>; | 296 | reg = <0x4a056000 0x1000>; |
@@ -1424,7 +1454,7 @@ | |||
1424 | compatible = "ti,dra7-d_can"; | 1454 | compatible = "ti,dra7-d_can"; |
1425 | ti,hwmods = "dcan1"; | 1455 | ti,hwmods = "dcan1"; |
1426 | reg = <0x4ae3c000 0x2000>; | 1456 | reg = <0x4ae3c000 0x2000>; |
1427 | syscon-raminit = <&dra7_ctrl_core 0x558 0>; | 1457 | syscon-raminit = <&scm_conf 0x558 0>; |
1428 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; | 1458 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
1429 | clocks = <&dcan1_sys_clk_mux>; | 1459 | clocks = <&dcan1_sys_clk_mux>; |
1430 | status = "disabled"; | 1460 | status = "disabled"; |
@@ -1434,7 +1464,7 @@ | |||
1434 | compatible = "ti,dra7-d_can"; | 1464 | compatible = "ti,dra7-d_can"; |
1435 | ti,hwmods = "dcan2"; | 1465 | ti,hwmods = "dcan2"; |
1436 | reg = <0x48480000 0x2000>; | 1466 | reg = <0x48480000 0x2000>; |
1437 | syscon-raminit = <&dra7_ctrl_core 0x558 1>; | 1467 | syscon-raminit = <&scm_conf 0x558 1>; |
1438 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; | 1468 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
1439 | clocks = <&sys_clkin1>; | 1469 | clocks = <&sys_clkin1>; |
1440 | status = "disabled"; | 1470 | status = "disabled"; |