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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2012-11-17 09:22:27 -0500
committerThomas Petazzoni <thomas.petazzoni@free-electrons.com>2012-11-20 08:46:50 -0500
commit5b03df9ace680d7cdd34a69dfd85ca5f74159d18 (patch)
tree76b36620fe07ceaa61a471e626f6cdfdf3cec93d /arch/arm/boot/dts/dove.dtsi
parent307c2bf467e3682c6df1b8186365224fd2d581d3 (diff)
ARM: dove: switch to DT clock providers
With true DT clock providers available switch Dove clock setup in DT- enabled boards. While AUXDATA can be removed completely from bus probing, some devices still don't know about DT at all. Therefore, some clock aliases are created until the devices also move to DT. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/dove.dtsi')
-rw-r--r--arch/arm/boot/dts/dove.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 5a00022383e7..b524ee377f83 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -31,6 +31,19 @@
31 reg = <0x20204 0x04>, <0x20214 0x04>; 31 reg = <0x20204 0x04>, <0x20214 0x04>;
32 }; 32 };
33 33
34 core_clk: core-clocks@d0214 {
35 compatible = "marvell,dove-core-clock";
36 reg = <0xd0214 0x4>;
37 #clock-cells = <1>;
38 };
39
40 gate_clk: clock-gating-control@d0038 {
41 compatible = "marvell,dove-gating-clock";
42 reg = <0xd0038 0x4>;
43 clocks = <&core_clk 0>;
44 #clock-cells = <1>;
45 };
46
34 uart0: serial@12000 { 47 uart0: serial@12000 {
35 compatible = "ns16550a"; 48 compatible = "ns16550a";
36 reg = <0x12000 0x100>; 49 reg = <0x12000 0x100>;
@@ -100,6 +113,7 @@
100 cell-index = <0>; 113 cell-index = <0>;
101 interrupts = <6>; 114 interrupts = <6>;
102 reg = <0x10600 0x28>; 115 reg = <0x10600 0x28>;
116 clocks = <&core_clk 0>;
103 status = "disabled"; 117 status = "disabled";
104 }; 118 };
105 119
@@ -110,6 +124,7 @@
110 cell-index = <1>; 124 cell-index = <1>;
111 interrupts = <5>; 125 interrupts = <5>;
112 reg = <0x14600 0x28>; 126 reg = <0x14600 0x28>;
127 clocks = <&core_clk 0>;
113 status = "disabled"; 128 status = "disabled";
114 }; 129 };
115 130
@@ -121,6 +136,7 @@
121 interrupts = <11>; 136 interrupts = <11>;
122 clock-frequency = <400000>; 137 clock-frequency = <400000>;
123 timeout-ms = <1000>; 138 timeout-ms = <1000>;
139 clocks = <&core_clk 0>;
124 status = "disabled"; 140 status = "disabled";
125 }; 141 };
126 142
@@ -128,6 +144,7 @@
128 compatible = "marvell,dove-sdhci"; 144 compatible = "marvell,dove-sdhci";
129 reg = <0x92000 0x100>; 145 reg = <0x92000 0x100>;
130 interrupts = <35>, <37>; 146 interrupts = <35>, <37>;
147 clocks = <&gate_clk 8>;
131 status = "disabled"; 148 status = "disabled";
132 }; 149 };
133 150
@@ -135,6 +152,7 @@
135 compatible = "marvell,dove-sdhci"; 152 compatible = "marvell,dove-sdhci";
136 reg = <0x90000 0x100>; 153 reg = <0x90000 0x100>;
137 interrupts = <36>, <38>; 154 interrupts = <36>, <38>;
155 clocks = <&gate_clk 9>;
138 status = "disabled"; 156 status = "disabled";
139 }; 157 };
140 158
@@ -142,6 +160,7 @@
142 compatible = "marvell,orion-sata"; 160 compatible = "marvell,orion-sata";
143 reg = <0xa0000 0x2400>; 161 reg = <0xa0000 0x2400>;
144 interrupts = <62>; 162 interrupts = <62>;
163 clocks = <&gate_clk 3>;
145 nr-ports = <1>; 164 nr-ports = <1>;
146 status = "disabled"; 165 status = "disabled";
147 }; 166 };
@@ -152,6 +171,7 @@
152 <0xc8000000 0x800>; 171 <0xc8000000 0x800>;
153 reg-names = "regs", "sram"; 172 reg-names = "regs", "sram";
154 interrupts = <31>; 173 interrupts = <31>;
174 clocks = <&gate_clk 15>;
155 status = "okay"; 175 status = "okay";
156 }; 176 };
157 }; 177 };