diff options
author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-05-20 10:48:10 -0400 |
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committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-10-29 14:44:45 -0400 |
commit | 652538c4d27df714efc4dd092e6defe87c0bbeb9 (patch) | |
tree | 5bd705cec6173dcf85cc22435747a4dea1c55252 /arch/arm/boot/dts/berlin2.dtsi | |
parent | 60daa9f71de148cbfc33187c2ce6d3dd80cf8fa0 (diff) |
ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD
Marvell Berlin BG2 has three, BG2CD just one pxav3 compatible
sdhci controllers, add them to the corresponding DT SoC
includes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2.dtsi')
-rw-r--r-- | arch/arm/boot/dts/berlin2.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index bbdad9510f19..20e7c394a008 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi | |||
@@ -53,6 +53,35 @@ | |||
53 | 53 | ||
54 | ranges = <0 0xf7000000 0x1000000>; | 54 | ranges = <0 0xf7000000 0x1000000>; |
55 | 55 | ||
56 | sdhci0: sdhci@ab0000 { | ||
57 | compatible = "mrvl,pxav3-mmc"; | ||
58 | reg = <0xab0000 0x200>; | ||
59 | clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; | ||
60 | clock-names = "io", "core"; | ||
61 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | ||
62 | status = "disabled"; | ||
63 | }; | ||
64 | |||
65 | sdhci1: sdhci@ab0800 { | ||
66 | compatible = "mrvl,pxav3-mmc"; | ||
67 | reg = <0xab0800 0x200>; | ||
68 | clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; | ||
69 | clock-names = "io", "core"; | ||
70 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | ||
71 | status = "disabled"; | ||
72 | }; | ||
73 | |||
74 | sdhci2: sdhci@ab1000 { | ||
75 | compatible = "mrvl,pxav3-mmc"; | ||
76 | reg = <0xab1000 0x200>; | ||
77 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | ||
78 | clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; | ||
79 | clock-names = "io", "core"; | ||
80 | pinctrl-0 = <&emmc_pmux>; | ||
81 | pinctrl-names = "default"; | ||
82 | status = "disabled"; | ||
83 | }; | ||
84 | |||
56 | l2: l2-cache-controller@ac0000 { | 85 | l2: l2-cache-controller@ac0000 { |
57 | compatible = "marvell,tauros3-cache", "arm,pl310-cache"; | 86 | compatible = "marvell,tauros3-cache", "arm,pl310-cache"; |
58 | reg = <0xac0000 0x1000>; | 87 | reg = <0xac0000 0x1000>; |
@@ -289,6 +318,11 @@ | |||
289 | reg = <0xea0000 0x400>; | 318 | reg = <0xea0000 0x400>; |
290 | clocks = <&refclk>; | 319 | clocks = <&refclk>; |
291 | clock-names = "refclk"; | 320 | clock-names = "refclk"; |
321 | |||
322 | emmc_pmux: emmc-pmux { | ||
323 | groups = "G26"; | ||
324 | function = "emmc"; | ||
325 | }; | ||
292 | }; | 326 | }; |
293 | 327 | ||
294 | apb@fc0000 { | 328 | apb@fc0000 { |