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authorAlex Elder <elder@linaro.org>2014-06-30 18:15:40 -0400
committerMatt Porter <mporter@linaro.org>2014-07-28 09:41:54 -0400
commit1d3138b75e3af493261c7a1e085b66b34c74dfbb (patch)
tree0bafc78fca1aa4e470d3b6899465c9bed4efd135 /arch/arm/boot/dts/bcm21664.dtsi
parenta62451c3f91af33e47a17f17ae65de76774b2854 (diff)
ARM: dts: enable SMP support for bcm21664
Define nodes representing the two Cortex A9 CPUs in a bcm21644 SoC. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/bcm21664.dtsi')
-rw-r--r--arch/arm/boot/dts/bcm21664.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 8b366822bb43..2016b72a8fb7 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -27,6 +27,25 @@
27 bootargs = "console=ttyS0,115200n8"; 27 bootargs = "console=ttyS0,115200n8";
28 }; 28 };
29 29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "brcm,bcm11351-cpu-method";
34 secondary-boot-reg = <0x35004178>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <1>;
46 };
47 };
48
30 gic: interrupt-controller@3ff00100 { 49 gic: interrupt-controller@3ff00100 {
31 compatible = "arm,cortex-a9-gic"; 50 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>; 51 #interrupt-cells = <3>;